mirror of
https://github.com/qmk/qmk_firmware.git
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Let's see how deep this rabbithole goes..
This commit is contained in:
Nick Brassel
parent
ea71945441
commit
ff7cc54fc5
@ -1,210 +1,288 @@
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/* Copyright 2018 Jack Humbert
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// Copyright 2024 Nick Brassel (@tzarc)
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* Copyright 2018 Yiancar
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// SPDX-License-Identifier: GPL-2.0-or-later
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* Copyright 2023 customMK
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* This library is only valid for STM32 processors.
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* This library follows the convention of the AVR i2c_master library.
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* As a result addresses are expected to be already shifted (addr << 1).
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* I2CD1 is the default driver which corresponds to pins B6 and B7. This
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* can be changed.
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* Please ensure that HAL_USE_I2C is TRUE in the halconf.h file and that
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* STM32_I2C_USE_I2C1 is TRUE in the mcuconf.h file. Pins B6 and B7 are used
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* but using any other I2C pins should be trivial.
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*/
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#include "i2c_master.h"
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#include "gpio.h"
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#include "chibios_config.h"
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#include <string.h>
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#include <ch.h>
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#include <hal.h>
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#include <hal.h>
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#include "i2c_master.h"
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#ifndef I2C1_SCL_PIN
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#ifndef I2C_MULTI_BUS
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# define I2C1_SCL_PIN B6
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#endif
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#ifndef I2C1_SDA_PIN
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# define I2C1_SDA_PIN B7
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#endif
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#ifdef USE_I2CV1
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# ifndef I2C1_SCL_PIN
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# ifndef I2C1_OPMODE
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# define I2C1_SCL_PIN B6
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# define I2C1_OPMODE OPMODE_I2C
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# endif
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# endif
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# ifndef I2C1_CLOCK_SPEED
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# ifndef I2C1_SDA_PIN
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# define I2C1_CLOCK_SPEED 100000 /* 400000 */
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# define I2C1_SDA_PIN B7
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# endif
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# endif
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# ifndef I2C1_DUTY_CYCLE
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# define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */
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# ifdef USE_I2CV1
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# endif
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# ifndef I2C1_OPMODE
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#else
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# define I2C1_OPMODE OPMODE_I2C
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# endif
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# ifndef I2C1_CLOCK_SPEED
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# define I2C1_CLOCK_SPEED 100000 /* 400000 */
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# endif
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# ifndef I2C1_DUTY_CYCLE
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# define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */
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# endif
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# else
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// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
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// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
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// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
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// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
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# ifndef I2C1_TIMINGR_PRESC
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# ifndef I2C1_TIMINGR_PRESC
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# define I2C1_TIMINGR_PRESC 0U
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# define I2C1_TIMINGR_PRESC 0U
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# endif
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# ifndef I2C1_TIMINGR_SCLDEL
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# define I2C1_TIMINGR_SCLDEL 7U
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# endif
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# ifndef I2C1_TIMINGR_SDADEL
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# define I2C1_TIMINGR_SDADEL 0U
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# endif
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# ifndef I2C1_TIMINGR_SCLH
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# define I2C1_TIMINGR_SCLH 38U
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# endif
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# ifndef I2C1_TIMINGR_SCLL
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# define I2C1_TIMINGR_SCLL 129U
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# endif
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# endif
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# endif
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# ifndef I2C1_TIMINGR_SCLDEL
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# define I2C1_TIMINGR_SCLDEL 7U
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# endif
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# ifndef I2C1_TIMINGR_SDADEL
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# define I2C1_TIMINGR_SDADEL 0U
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# endif
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# ifndef I2C1_TIMINGR_SCLH
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# define I2C1_TIMINGR_SCLH 38U
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# endif
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# ifndef I2C1_TIMINGR_SCLL
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# define I2C1_TIMINGR_SCLL 129U
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# endif
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#endif
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#ifndef I2C_DRIVER
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# ifndef I2C_DRIVER
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# define I2C_DRIVER I2CD1
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# define I2C_DRIVER I2CD1
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#endif
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# endif
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#ifdef USE_GPIOV1
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# ifdef USE_GPIOV1
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# ifndef I2C1_SCL_PAL_MODE
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# ifndef I2C1_SCL_PAL_MODE
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# define I2C1_SCL_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
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# define I2C1_SCL_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
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# endif
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# endif
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# ifndef I2C1_SDA_PAL_MODE
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# ifndef I2C1_SDA_PAL_MODE
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# define I2C1_SDA_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
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# define I2C1_SDA_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
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# endif
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# endif
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#else
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# else
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// The default PAL alternate modes are used to signal that the pins are used for I2C
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// The default PAL alternate modes are used to signal that the pins are used for I2C
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# ifndef I2C1_SCL_PAL_MODE
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# ifndef I2C1_SCL_PAL_MODE
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# define I2C1_SCL_PAL_MODE 4
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# define I2C1_SCL_PAL_MODE 4
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# endif
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# ifndef I2C1_SDA_PAL_MODE
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# define I2C1_SDA_PAL_MODE 4
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# endif
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# endif
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# endif
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# ifndef I2C1_SDA_PAL_MODE
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# define I2C1_SDA_PAL_MODE 4
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# endif
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#endif
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static const I2CConfig i2cconfig = {
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# define _I2Cx_DRIVER I2C_DRIVER
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#if defined(USE_I2CV1_CONTRIB)
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# define _I2Cx_SCL_PIN I2C1_SCL_PIN
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I2C1_CLOCK_SPEED,
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# define _I2Cx_SDA_PIN I2C1_SDA_PIN
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#elif defined(USE_I2CV1)
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# define _I2Cx_OPMODE I2C1_OPMODE
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I2C1_OPMODE,
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# define _I2Cx_CLOCK_SPEED I2C1_CLOCK_SPEED
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I2C1_CLOCK_SPEED,
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# define _I2Cx_DUTY_CYCLE I2C1_DUTY_CYCLE
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I2C1_DUTY_CYCLE,
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# define _I2Cx_TIMINGR_PRESC I2C1_TIMINGR_PRESC
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#elif defined(WB32F3G71xx) || defined(WB32FQ95xx)
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# define _I2Cx_TIMINGR_SCLDEL I2C1_TIMINGR_SCLDEL
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I2C1_OPMODE,
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# define _I2Cx_TIMINGR_SDADEL I2C1_TIMINGR_SDADEL
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I2C1_CLOCK_SPEED,
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# define _I2Cx_TIMINGR_SCLH I2C1_TIMINGR_SCLH
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#else
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# define _I2Cx_TIMINGR_SCLL I2C1_TIMINGR_SCLL
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// This configures the I2C clock to 400khz assuming a 72Mhz clock
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# define _I2Cx_SCL_PAL_MODE I2C1_SCL_PAL_MODE
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// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
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# define _I2Cx_SDA_PAL_MODE I2C1_SDA_PAL_MODE
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STM32_TIMINGR_PRESC(I2C1_TIMINGR_PRESC) | STM32_TIMINGR_SCLDEL(I2C1_TIMINGR_SCLDEL) | STM32_TIMINGR_SDADEL(I2C1_TIMINGR_SDADEL) | STM32_TIMINGR_SCLH(I2C1_TIMINGR_SCLH) | STM32_TIMINGR_SCLL(I2C1_TIMINGR_SCLL), 0, 0
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#endif
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};
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/**
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# define _i2cx_config i2cconfig
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* @brief Handles any I2C error condition by stopping the I2C peripheral and
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# define _i2cx_epilogue i2c_epilogue
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* aborting any ongoing transactions. Furthermore ChibiOS status codes are
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# define _i2cx_init i2c_init
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* converted into QMK codes.
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# define _i2cx_transmit i2c_transmit
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*
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# define _i2cx_receive i2c_receive
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* @param status ChibiOS specific I2C status code
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# define _i2cx_write_register i2c_write_register
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* @return i2c_status_t QMK specific I2C status code
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# define _i2cx_write_register16 i2c_write_register16
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*/
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# define _i2cx_read_register i2c_read_register
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static i2c_status_t i2c_epilogue(const msg_t status) {
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# define _i2cx_read_register16 i2c_read_register16
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if (status == MSG_OK) {
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# define _i2cx_ping_address i2c_ping_address
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return I2C_STATUS_SUCCESS;
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}
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// From ChibiOS HAL: "After a timeout the driver must be stopped and
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# include "i2c_master.impl.c"
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// restarted because the bus is in an uncertain state." We also issue that
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// hard stop in case of any error.
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i2cStop(&I2C_DRIVER);
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return status == MSG_TIMEOUT ? I2C_STATUS_TIMEOUT : I2C_STATUS_ERROR;
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#else // I2C_MULTI_BUS
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// Ensure we aren't overriding I2C APIs with a default bus when we #include the impl
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# undef i2c_init
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# undef i2c_transmit
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# undef i2c_receive
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# undef i2c_write_register
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# undef i2c_write_register16
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# undef i2c_read_register
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# undef i2c_read_register16
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# undef i2c_ping_address
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# ifdef HAS_I2C0
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# undef _i2cx_config
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# undef _i2cx_epilogue
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# undef _i2cx_init
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# undef _i2cx_transmit
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# undef _i2cx_receive
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# undef _i2cx_write_register
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# undef _i2cx_write_register16
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# undef _i2cx_read_register
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# undef _i2cx_read_register16
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# undef _i2cx_ping_address
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# define _i2cx_config i2c0config
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# define _i2cx_epilogue i2c0_epilogue
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# define _i2cx_init i2c0_init
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# define _i2cx_transmit i2c0_transmit
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# define _i2cx_receive i2c0_receive
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# define _i2cx_write_register i2c0_write_register
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# define _i2cx_write_register16 i2c0_write_register16
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# define _i2cx_read_register i2c0_read_register
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# define _i2cx_read_register16 i2c0_read_register16
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# define _i2cx_ping_address i2c0_ping_address
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# undef _I2Cx_DRIVER
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# undef _I2Cx_SCL_PIN
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# undef _I2Cx_SDA_PIN
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# undef _I2Cx_OPMODE
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# undef _I2Cx_CLOCK_SPEED
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# undef _I2Cx_DUTY_CYCLE
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# undef _I2Cx_TIMINGR_PRESC
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# undef _I2Cx_TIMINGR_SCLDEL
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# undef _I2Cx_TIMINGR_SDADEL
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# undef _I2Cx_TIMINGR_SCLH
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# undef _I2Cx_TIMINGR_SCLL
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# undef _I2Cx_SCL_PAL_MODE
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# undef _I2Cx_SDA_PAL_MODE
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# define _I2Cx_DRIVER I2CD0
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# define _I2Cx_SCL_PIN I2C0_SCL_PIN
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# define _I2Cx_SDA_PIN I2C0_SDA_PIN
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# define _I2Cx_OPMODE I2C0_OPMODE
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# define _I2Cx_CLOCK_SPEED I2C0_CLOCK_SPEED
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# define _I2Cx_DUTY_CYCLE I2C0_DUTY_CYCLE
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# define _I2Cx_TIMINGR_PRESC I2C0_TIMINGR_PRESC
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# define _I2Cx_TIMINGR_SCLDEL I2C0_TIMINGR_SCLDEL
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# define _I2Cx_TIMINGR_SDADEL I2C0_TIMINGR_SDADEL
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# define _I2Cx_TIMINGR_SCLH I2C0_TIMINGR_SCLH
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# define _I2Cx_TIMINGR_SCLL I2C0_TIMINGR_SCLL
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# define _I2Cx_SCL_PAL_MODE I2C0_SCL_PAL_MODE
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# define _I2Cx_SDA_PAL_MODE I2C0_SDA_PAL_MODE
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# include "i2c_master.impl.c"
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# endif // HAS_I2C0
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# ifdef HAS_I2C1
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# undef _I2Cx_DRIVER
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# undef _i2cx_config
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# undef _i2cx_epilogue
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# undef _i2cx_init
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# undef _i2cx_transmit
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# undef _i2cx_receive
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# undef _i2cx_write_register
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# undef _i2cx_write_register16
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# undef _i2cx_read_register
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# undef _i2cx_read_register16
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# undef _i2cx_ping_address
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||||||
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# define _i2cx_config i2c1config
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# define _i2cx_epilogue i2c1_epilogue
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# define _i2cx_init i2c1_init
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# define _i2cx_transmit i2c1_transmit
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# define _i2cx_receive i2c1_receive
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||||||
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# define _i2cx_write_register i2c1_write_register
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# define _i2cx_write_register16 i2c1_write_register16
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||||||
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# define _i2cx_read_register i2c1_read_register
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||||||
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# define _i2cx_read_register16 i2c1_read_register16
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||||||
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# define _i2cx_ping_address i2c1_ping_address
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||||||
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||||||
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# undef _I2Cx_DRIVER
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||||||
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# undef _I2Cx_SCL_PIN
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||||||
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# undef _I2Cx_SDA_PIN
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||||||
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# undef _I2Cx_OPMODE
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||||||
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# undef _I2Cx_CLOCK_SPEED
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||||||
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# undef _I2Cx_DUTY_CYCLE
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||||||
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# undef _I2Cx_TIMINGR_PRESC
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||||||
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# undef _I2Cx_TIMINGR_SCLDEL
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||||||
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# undef _I2Cx_TIMINGR_SDADEL
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||||||
|
# undef _I2Cx_TIMINGR_SCLH
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||||||
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# undef _I2Cx_TIMINGR_SCLL
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||||||
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# undef _I2Cx_SCL_PAL_MODE
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||||||
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# undef _I2Cx_SDA_PAL_MODE
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||||||
|
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||||||
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# define _I2Cx_DRIVER I2CD1
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||||||
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# define _I2Cx_SCL_PIN I2C1_SCL_PIN
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# define _I2Cx_SDA_PIN I2C1_SDA_PIN
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||||||
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# define _I2Cx_OPMODE I2C1_OPMODE
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||||||
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# define _I2Cx_CLOCK_SPEED I2C1_CLOCK_SPEED
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||||||
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# define _I2Cx_DUTY_CYCLE I2C1_DUTY_CYCLE
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||||||
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# define _I2Cx_TIMINGR_PRESC I2C1_TIMINGR_PRESC
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||||||
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# define _I2Cx_TIMINGR_SCLDEL I2C1_TIMINGR_SCLDEL
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||||||
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# define _I2Cx_TIMINGR_SDADEL I2C1_TIMINGR_SDADEL
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||||||
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# define _I2Cx_TIMINGR_SCLH I2C1_TIMINGR_SCLH
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||||||
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# define _I2Cx_TIMINGR_SCLL I2C1_TIMINGR_SCLL
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||||||
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# define _I2Cx_SCL_PAL_MODE I2C1_SCL_PAL_MODE
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||||||
|
# define _I2Cx_SDA_PAL_MODE I2C1_SDA_PAL_MODE
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||||||
|
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||||||
|
# include "i2c_master.impl.c"
|
||||||
|
|
||||||
|
# endif // HAS_I2C1
|
||||||
|
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||||||
|
# ifdef HAS_I2C2
|
||||||
|
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||||||
|
# undef _I2Cx_DRIVER
|
||||||
|
# undef _i2cx_config
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||||||
|
# undef _i2cx_epilogue
|
||||||
|
# undef _i2cx_init
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||||||
|
# undef _i2cx_transmit
|
||||||
|
# undef _i2cx_receive
|
||||||
|
# undef _i2cx_write_register
|
||||||
|
# undef _i2cx_write_register16
|
||||||
|
# undef _i2cx_read_register
|
||||||
|
# undef _i2cx_read_register16
|
||||||
|
# undef _i2cx_ping_address
|
||||||
|
|
||||||
|
# define _i2cx_config i2c2config
|
||||||
|
# define _i2cx_epilogue i2c2_epilogue
|
||||||
|
# define _i2cx_init i2c2_init
|
||||||
|
# define _i2cx_transmit i2c2_transmit
|
||||||
|
# define _i2cx_receive i2c2_receive
|
||||||
|
# define _i2cx_write_register i2c2_write_register
|
||||||
|
# define _i2cx_write_register16 i2c2_write_register16
|
||||||
|
# define _i2cx_read_register i2c2_read_register
|
||||||
|
# define _i2cx_read_register16 i2c2_read_register16
|
||||||
|
# define _i2cx_ping_address i2c2_ping_address
|
||||||
|
|
||||||
|
# undef _I2Cx_DRIVER
|
||||||
|
# undef _I2Cx_SCL_PIN
|
||||||
|
# undef _I2Cx_SDA_PIN
|
||||||
|
# undef _I2Cx_OPMODE
|
||||||
|
# undef _I2Cx_CLOCK_SPEED
|
||||||
|
# undef _I2Cx_DUTY_CYCLE
|
||||||
|
# undef _I2Cx_TIMINGR_PRESC
|
||||||
|
# undef _I2Cx_TIMINGR_SCLDEL
|
||||||
|
# undef _I2Cx_TIMINGR_SDADEL
|
||||||
|
# undef _I2Cx_TIMINGR_SCLH
|
||||||
|
# undef _I2Cx_TIMINGR_SCLL
|
||||||
|
# undef _I2Cx_SCL_PAL_MODE
|
||||||
|
# undef _I2Cx_SDA_PAL_MODE
|
||||||
|
|
||||||
|
# define _I2Cx_DRIVER I2CD2
|
||||||
|
# define _I2Cx_SCL_PIN I2C2_SCL_PIN
|
||||||
|
# define _I2Cx_SDA_PIN I2C2_SDA_PIN
|
||||||
|
# define _I2Cx_OPMODE I2C2_OPMODE
|
||||||
|
# define _I2Cx_CLOCK_SPEED I2C2_CLOCK_SPEED
|
||||||
|
# define _I2Cx_DUTY_CYCLE I2C2_DUTY_CYCLE
|
||||||
|
# define _I2Cx_TIMINGR_PRESC I2C2_TIMINGR_PRESC
|
||||||
|
# define _I2Cx_TIMINGR_SCLDEL I2C2_TIMINGR_SCLDEL
|
||||||
|
# define _I2Cx_TIMINGR_SDADEL I2C2_TIMINGR_SDADEL
|
||||||
|
# define _I2Cx_TIMINGR_SCLH I2C2_TIMINGR_SCLH
|
||||||
|
# define _I2Cx_TIMINGR_SCLL I2C2_TIMINGR_SCLL
|
||||||
|
# define _I2Cx_SCL_PAL_MODE I2C2_SCL_PAL_MODE
|
||||||
|
# define _I2Cx_SDA_PAL_MODE I2C2_SDA_PAL_MODE
|
||||||
|
|
||||||
|
# include "i2c_master.impl.c"
|
||||||
|
|
||||||
|
# endif // HAS_I2C2
|
||||||
|
|
||||||
|
void i2c_init(void) {
|
||||||
|
# ifdef HAS_I2C0
|
||||||
|
i2c0_init();
|
||||||
|
# endif // HAS_I2C0
|
||||||
|
# ifdef HAS_I2C1
|
||||||
|
i2c1_init();
|
||||||
|
# endif // HAS_I2C1
|
||||||
|
# ifdef HAS_I2C2
|
||||||
|
i2c2_init();
|
||||||
|
# endif // HAS_I2C2
|
||||||
}
|
}
|
||||||
|
|
||||||
__attribute__((weak)) void i2c_init(void) {
|
#endif // I2C_MULTI_BUS
|
||||||
static bool is_initialised = false;
|
|
||||||
if (!is_initialised) {
|
|
||||||
is_initialised = true;
|
|
||||||
|
|
||||||
// Try releasing special pins for a short time
|
|
||||||
palSetLineMode(I2C1_SCL_PIN, PAL_MODE_INPUT);
|
|
||||||
palSetLineMode(I2C1_SDA_PIN, PAL_MODE_INPUT);
|
|
||||||
|
|
||||||
chThdSleepMilliseconds(10);
|
|
||||||
#if defined(USE_GPIOV1)
|
|
||||||
palSetLineMode(I2C1_SCL_PIN, I2C1_SCL_PAL_MODE);
|
|
||||||
palSetLineMode(I2C1_SDA_PIN, I2C1_SDA_PAL_MODE);
|
|
||||||
#else
|
|
||||||
palSetLineMode(I2C1_SCL_PIN, PAL_MODE_ALTERNATE(I2C1_SCL_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN);
|
|
||||||
palSetLineMode(I2C1_SDA_PIN, PAL_MODE_ALTERNATE(I2C1_SDA_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout) {
|
|
||||||
i2cStart(&I2C_DRIVER, &i2cconfig);
|
|
||||||
msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (address >> 1), data, length, 0, 0, TIME_MS2I(timeout));
|
|
||||||
return i2c_epilogue(status);
|
|
||||||
}
|
|
||||||
|
|
||||||
i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout) {
|
|
||||||
i2cStart(&I2C_DRIVER, &i2cconfig);
|
|
||||||
msg_t status = i2cMasterReceiveTimeout(&I2C_DRIVER, (address >> 1), data, length, TIME_MS2I(timeout));
|
|
||||||
return i2c_epilogue(status);
|
|
||||||
}
|
|
||||||
|
|
||||||
i2c_status_t i2c_write_register(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout) {
|
|
||||||
i2cStart(&I2C_DRIVER, &i2cconfig);
|
|
||||||
|
|
||||||
uint8_t complete_packet[length + 1];
|
|
||||||
for (uint16_t i = 0; i < length; i++) {
|
|
||||||
complete_packet[i + 1] = data[i];
|
|
||||||
}
|
|
||||||
complete_packet[0] = regaddr;
|
|
||||||
|
|
||||||
msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (devaddr >> 1), complete_packet, length + 1, 0, 0, TIME_MS2I(timeout));
|
|
||||||
return i2c_epilogue(status);
|
|
||||||
}
|
|
||||||
|
|
||||||
i2c_status_t i2c_write_register16(uint8_t devaddr, uint16_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout) {
|
|
||||||
i2cStart(&I2C_DRIVER, &i2cconfig);
|
|
||||||
|
|
||||||
uint8_t complete_packet[length + 2];
|
|
||||||
for (uint16_t i = 0; i < length; i++) {
|
|
||||||
complete_packet[i + 2] = data[i];
|
|
||||||
}
|
|
||||||
complete_packet[0] = regaddr >> 8;
|
|
||||||
complete_packet[1] = regaddr & 0xFF;
|
|
||||||
|
|
||||||
msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (devaddr >> 1), complete_packet, length + 2, 0, 0, TIME_MS2I(timeout));
|
|
||||||
return i2c_epilogue(status);
|
|
||||||
}
|
|
||||||
|
|
||||||
i2c_status_t i2c_read_register(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout) {
|
|
||||||
i2cStart(&I2C_DRIVER, &i2cconfig);
|
|
||||||
msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (devaddr >> 1), ®addr, 1, data, length, TIME_MS2I(timeout));
|
|
||||||
return i2c_epilogue(status);
|
|
||||||
}
|
|
||||||
|
|
||||||
i2c_status_t i2c_read_register16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout) {
|
|
||||||
i2cStart(&I2C_DRIVER, &i2cconfig);
|
|
||||||
uint8_t register_packet[2] = {regaddr >> 8, regaddr & 0xFF};
|
|
||||||
msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (devaddr >> 1), register_packet, 2, data, length, TIME_MS2I(timeout));
|
|
||||||
return i2c_epilogue(status);
|
|
||||||
}
|
|
||||||
|
|
||||||
__attribute__((weak)) i2c_status_t i2c_ping_address(uint8_t address, uint16_t timeout) {
|
|
||||||
// ChibiOS does not provide low level enough control to check for an ack.
|
|
||||||
// Best effort instead tries reading register 0 which will either succeed or timeout.
|
|
||||||
// This approach may produce false negative results for I2C devices that do not respond to a register 0 read request.
|
|
||||||
uint8_t data = 0;
|
|
||||||
return i2c_read_register(address, 0, &data, sizeof(data), timeout);
|
|
||||||
}
|
|
||||||
|
|||||||
@ -1,5 +1,6 @@
|
|||||||
/* Copyright 2018 Jack Humbert
|
/* Copyright 2018 Jack Humbert
|
||||||
* Copyright 2018 Yiancar
|
* Copyright 2018 Yiancar
|
||||||
|
* Copyright 2024 Nick Brassel (@tzarc)
|
||||||
*
|
*
|
||||||
* This program is free software: you can redistribute it and/or modify
|
* This program is free software: you can redistribute it and/or modify
|
||||||
* it under the terms of the GNU General Public License as published by
|
* it under the terms of the GNU General Public License as published by
|
||||||
@ -25,6 +26,7 @@
|
|||||||
#pragma once
|
#pragma once
|
||||||
|
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
#include <hal.h>
|
||||||
|
|
||||||
// ### DEPRECATED - DO NOT USE ###
|
// ### DEPRECATED - DO NOT USE ###
|
||||||
#define i2c_writeReg(devaddr, regaddr, data, length, timeout) i2c_write_register(devaddr, regaddr, data, length, timeout)
|
#define i2c_writeReg(devaddr, regaddr, data, length, timeout) i2c_write_register(devaddr, regaddr, data, length, timeout)
|
||||||
@ -39,6 +41,8 @@ typedef int16_t i2c_status_t;
|
|||||||
#define I2C_STATUS_ERROR (-1)
|
#define I2C_STATUS_ERROR (-1)
|
||||||
#define I2C_STATUS_TIMEOUT (-2)
|
#define I2C_STATUS_TIMEOUT (-2)
|
||||||
|
|
||||||
|
#ifndef I2C_MULTI_BUS
|
||||||
|
|
||||||
void i2c_init(void);
|
void i2c_init(void);
|
||||||
i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout);
|
i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
|
i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
@ -47,3 +51,83 @@ i2c_status_t i2c_write_register16(uint8_t devaddr, uint16_t regaddr, const uint8
|
|||||||
i2c_status_t i2c_read_register(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
|
i2c_status_t i2c_read_register(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
i2c_status_t i2c_read_register16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
|
i2c_status_t i2c_read_register16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
i2c_status_t i2c_ping_address(uint8_t address, uint16_t timeout);
|
i2c_status_t i2c_ping_address(uint8_t address, uint16_t timeout);
|
||||||
|
|
||||||
|
#else
|
||||||
|
|
||||||
|
# if defined(RP_I2C_USE_I2C0) && RP_I2C_USE_I2C0 == TRUE
|
||||||
|
# define HAS_I2C0
|
||||||
|
# endif
|
||||||
|
|
||||||
|
# if (defined(STM32_I2C_USE_I2C1) && STM32_I2C_USE_I2C1 == TRUE) || (defined(RP_I2C_USE_I2C1) && RP_I2C_USE_I2C1 == TRUE)
|
||||||
|
# define HAS_I2C1
|
||||||
|
# endif
|
||||||
|
|
||||||
|
# if defined(STM32_I2C_USE_I2C2) && STM32_I2C_USE_I2C2 == TRUE
|
||||||
|
# define HAS_I2C2
|
||||||
|
# endif
|
||||||
|
|
||||||
|
# ifdef HAS_I2C0
|
||||||
|
void i2c0_init(void);
|
||||||
|
i2c_status_t i2c0_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
|
i2c_status_t i2c0_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
|
i2c_status_t i2c0_write_register(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
|
i2c_status_t i2c0_write_register16(uint8_t devaddr, uint16_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
|
i2c_status_t i2c0_read_register(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
|
i2c_status_t i2c0_read_register16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
|
i2c_status_t i2c0_ping_address(uint8_t address, uint16_t timeout);
|
||||||
|
# endif // HAS_I2C0
|
||||||
|
|
||||||
|
# ifdef HAS_I2C1
|
||||||
|
void i2c1_init(void);
|
||||||
|
i2c_status_t i2c1_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
|
i2c_status_t i2c1_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
|
i2c_status_t i2c1_write_register(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
|
i2c_status_t i2c1_write_register16(uint8_t devaddr, uint16_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
|
i2c_status_t i2c1_read_register(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
|
i2c_status_t i2c1_read_register16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
|
i2c_status_t i2c1_ping_address(uint8_t address, uint16_t timeout);
|
||||||
|
# endif // HAS_I2C1
|
||||||
|
|
||||||
|
# ifdef HAS_I2C2
|
||||||
|
void i2c2_init(void);
|
||||||
|
i2c_status_t i2c2_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
|
i2c_status_t i2c2_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
|
i2c_status_t i2c2_write_register(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
|
i2c_status_t i2c2_write_register16(uint8_t devaddr, uint16_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
|
i2c_status_t i2c2_read_register(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
|
i2c_status_t i2c2_read_register16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
|
||||||
|
i2c_status_t i2c2_ping_address(uint8_t address, uint16_t timeout);
|
||||||
|
# endif // HAS_I2C2
|
||||||
|
|
||||||
|
# ifdef I2C_DEFAULT_BUS
|
||||||
|
# if I2C_DEFAULT_BUS == 0
|
||||||
|
# define i2c_init i2c0_init
|
||||||
|
# define i2c_transmit i2c0_transmit
|
||||||
|
# define i2c_receive i2c0_receive
|
||||||
|
# define i2c_write_register i2c0_write_register
|
||||||
|
# define i2c_write_register16 i2c0_write_register16
|
||||||
|
# define i2c_read_register i2c0_read_register
|
||||||
|
# define i2c_read_register16 i2c0_read_register16
|
||||||
|
# define i2c_ping_address i2c0_ping_address
|
||||||
|
# elif I2C_DEFAULT_BUS == 1
|
||||||
|
# define i2c_init i2c1_init
|
||||||
|
# define i2c_transmit i2c1_transmit
|
||||||
|
# define i2c_receive i2c1_receive
|
||||||
|
# define i2c_write_register i2c1_write_register
|
||||||
|
# define i2c_write_register16 i2c1_write_register16
|
||||||
|
# define i2c_read_register i2c1_read_register
|
||||||
|
# define i2c_read_register16 i2c1_read_register16
|
||||||
|
# define i2c_ping_address i2c1_ping_address
|
||||||
|
# elif I2C_DEFAULT_BUS == 2
|
||||||
|
# define i2c_init i2c2_init
|
||||||
|
# define i2c_transmit i2c2_transmit
|
||||||
|
# define i2c_receive i2c2_receive
|
||||||
|
# define i2c_write_register i2c2_write_register
|
||||||
|
# define i2c_write_register16 i2c2_write_register16
|
||||||
|
# define i2c_read_register i2c2_read_register
|
||||||
|
# define i2c_read_register16 i2c2_read_register16
|
||||||
|
# define i2c_ping_address i2c2_ping_address
|
||||||
|
# endif // I2C_DEFAULT_BUS == ?
|
||||||
|
# endif // I2C_DEFAULT_BUS
|
||||||
|
|
||||||
|
#endif // I2C_MULTI_BUS
|
||||||
|
|||||||
152
platforms/chibios/drivers/i2c_master.impl.c
Normal file
152
platforms/chibios/drivers/i2c_master.impl.c
Normal file
@ -0,0 +1,152 @@
|
|||||||
|
/* Copyright 2018 Jack Humbert
|
||||||
|
* Copyright 2018 Yiancar
|
||||||
|
* Copyright 2023 customMK
|
||||||
|
*
|
||||||
|
* This program is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* This library is only valid for STM32 processors.
|
||||||
|
* This library follows the convention of the AVR i2c_master library.
|
||||||
|
* As a result addresses are expected to be already shifted (addr << 1).
|
||||||
|
* I2CD1 is the default driver which corresponds to pins B6 and B7. This
|
||||||
|
* can be changed.
|
||||||
|
* Please ensure that HAL_USE_I2C is TRUE in the halconf.h file and that
|
||||||
|
* STM32_I2C_USE_I2C1 is TRUE in the mcuconf.h file. Pins B6 and B7 are used
|
||||||
|
* but using any other I2C pins should be trivial.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "i2c_master.h"
|
||||||
|
#include "gpio.h"
|
||||||
|
#include "chibios_config.h"
|
||||||
|
#include <string.h>
|
||||||
|
#include <ch.h>
|
||||||
|
#include <hal.h>
|
||||||
|
|
||||||
|
static const I2CConfig _i2cx_config = {
|
||||||
|
#if defined(USE_I2CV1_CONTRIB)
|
||||||
|
_I2Cx_CLOCK_SPEED,
|
||||||
|
#elif defined(USE_I2CV1)
|
||||||
|
_I2Cx_OPMODE,
|
||||||
|
_I2Cx_CLOCK_SPEED,
|
||||||
|
_I2Cx_DUTY_CYCLE,
|
||||||
|
#elif defined(WB32F3G71xx) || defined(WB32FQ95xx)
|
||||||
|
_I2Cx_OPMODE,
|
||||||
|
_I2Cx_CLOCK_SPEED,
|
||||||
|
#else
|
||||||
|
// This configures the I2C clock to 400khz assuming a 72Mhz clock
|
||||||
|
// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
|
||||||
|
STM32_TIMINGR_PRESC(_I2Cx_TIMINGR_PRESC) | STM32_TIMINGR_SCLDEL(_I2Cx_TIMINGR_SCLDEL) | STM32_TIMINGR_SDADEL(_I2Cx_TIMINGR_SDADEL) | STM32_TIMINGR_SCLH(_I2Cx_TIMINGR_SCLH) | STM32_TIMINGR_SCLL(_I2Cx_TIMINGR_SCLL), 0, 0
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Handles any I2C error condition by stopping the I2C peripheral and
|
||||||
|
* aborting any ongoing transactions. Furthermore ChibiOS status codes are
|
||||||
|
* converted into QMK codes.
|
||||||
|
*
|
||||||
|
* @param status ChibiOS specific I2C status code
|
||||||
|
* @return i2c_status_t QMK specific I2C status code
|
||||||
|
*/
|
||||||
|
static i2c_status_t _i2cx_epilogue(const msg_t status) {
|
||||||
|
if (status == MSG_OK) {
|
||||||
|
return I2C_STATUS_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
// From ChibiOS HAL: "After a timeout the driver must be stopped and
|
||||||
|
// restarted because the bus is in an uncertain state." We also issue that
|
||||||
|
// hard stop in case of any error.
|
||||||
|
i2cStop(&_I2Cx_DRIVER);
|
||||||
|
|
||||||
|
return status == MSG_TIMEOUT ? I2C_STATUS_TIMEOUT : I2C_STATUS_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__((weak)) void _i2cx_init(void) {
|
||||||
|
static bool is_initialised = false;
|
||||||
|
if (!is_initialised) {
|
||||||
|
is_initialised = true;
|
||||||
|
|
||||||
|
// Try releasing special pins for a short time
|
||||||
|
palSetLineMode(_I2Cx_SCL_PIN, PAL_MODE_INPUT);
|
||||||
|
palSetLineMode(_I2Cx_SDA_PIN, PAL_MODE_INPUT);
|
||||||
|
|
||||||
|
chThdSleepMilliseconds(10);
|
||||||
|
#if defined(USE_GPIOV1)
|
||||||
|
palSetLineMode(_I2Cx_SCL_PIN, _I2Cx_SCL_PAL_MODE);
|
||||||
|
palSetLineMode(_I2Cx_SDA_PIN, _I2Cx_SDA_PAL_MODE);
|
||||||
|
#else
|
||||||
|
palSetLineMode(_I2Cx_SCL_PIN, PAL_MODE_ALTERNATE(_I2Cx_SCL_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN);
|
||||||
|
palSetLineMode(_I2Cx_SDA_PIN, PAL_MODE_ALTERNATE(_I2Cx_SDA_PAL_MODE) | PAL_OUTPUT_TYPE_OPENDRAIN);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
i2c_status_t _i2cx_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout) {
|
||||||
|
i2cStart(&_I2Cx_DRIVER, &_i2cx_config);
|
||||||
|
msg_t status = i2cMasterTransmitTimeout(&_I2Cx_DRIVER, (address >> 1), data, length, 0, 0, TIME_MS2I(timeout));
|
||||||
|
return _i2cx_epilogue(status);
|
||||||
|
}
|
||||||
|
|
||||||
|
i2c_status_t _i2cx_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout) {
|
||||||
|
i2cStart(&_I2Cx_DRIVER, &_i2cx_config);
|
||||||
|
msg_t status = i2cMasterReceiveTimeout(&_I2Cx_DRIVER, (address >> 1), data, length, TIME_MS2I(timeout));
|
||||||
|
return _i2cx_epilogue(status);
|
||||||
|
}
|
||||||
|
|
||||||
|
i2c_status_t _i2cx_write_register(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout) {
|
||||||
|
i2cStart(&_I2Cx_DRIVER, &_i2cx_config);
|
||||||
|
|
||||||
|
uint8_t complete_packet[length + 1];
|
||||||
|
for (uint16_t i = 0; i < length; i++) {
|
||||||
|
complete_packet[i + 1] = data[i];
|
||||||
|
}
|
||||||
|
complete_packet[0] = regaddr;
|
||||||
|
|
||||||
|
msg_t status = i2cMasterTransmitTimeout(&_I2Cx_DRIVER, (devaddr >> 1), complete_packet, length + 1, 0, 0, TIME_MS2I(timeout));
|
||||||
|
return _i2cx_epilogue(status);
|
||||||
|
}
|
||||||
|
|
||||||
|
i2c_status_t _i2cx_write_register16(uint8_t devaddr, uint16_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout) {
|
||||||
|
i2cStart(&_I2Cx_DRIVER, &_i2cx_config);
|
||||||
|
|
||||||
|
uint8_t complete_packet[length + 2];
|
||||||
|
for (uint16_t i = 0; i < length; i++) {
|
||||||
|
complete_packet[i + 2] = data[i];
|
||||||
|
}
|
||||||
|
complete_packet[0] = regaddr >> 8;
|
||||||
|
complete_packet[1] = regaddr & 0xFF;
|
||||||
|
|
||||||
|
msg_t status = i2cMasterTransmitTimeout(&_I2Cx_DRIVER, (devaddr >> 1), complete_packet, length + 2, 0, 0, TIME_MS2I(timeout));
|
||||||
|
return _i2cx_epilogue(status);
|
||||||
|
}
|
||||||
|
|
||||||
|
i2c_status_t _i2cx_read_register(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout) {
|
||||||
|
i2cStart(&_I2Cx_DRIVER, &_i2cx_config);
|
||||||
|
msg_t status = i2cMasterTransmitTimeout(&_I2Cx_DRIVER, (devaddr >> 1), ®addr, 1, data, length, TIME_MS2I(timeout));
|
||||||
|
return _i2cx_epilogue(status);
|
||||||
|
}
|
||||||
|
|
||||||
|
i2c_status_t _i2cx_read_register16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout) {
|
||||||
|
i2cStart(&_I2Cx_DRIVER, &_i2cx_config);
|
||||||
|
uint8_t register_packet[2] = {regaddr >> 8, regaddr & 0xFF};
|
||||||
|
msg_t status = i2cMasterTransmitTimeout(&_I2Cx_DRIVER, (devaddr >> 1), register_packet, 2, data, length, TIME_MS2I(timeout));
|
||||||
|
return _i2cx_epilogue(status);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__((weak)) i2c_status_t _i2cx_ping_address(uint8_t address, uint16_t timeout) {
|
||||||
|
// ChibiOS does not provide low level enough control to check for an ack.
|
||||||
|
// Best effort instead tries reading register 0 which will either succeed or timeout.
|
||||||
|
// This approach may produce false negative results for I2C devices that do not respond to a register 0 read request.
|
||||||
|
uint8_t data = 0;
|
||||||
|
return _i2cx_read_register(address, 0, &data, sizeof(data), timeout);
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue
Block a user