mirror of
https://github.com/qmk/qmk_firmware.git
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chibios: boards: add generic STM32G0B1xB board
Signed-off-by: Stefan Kerkmann <karlk90@pm.me>
This commit is contained in:
Stefan Kerkmann
parent
5ab408aef7
commit
ee2076e8ab
266
platforms/chibios/boards/GENERIC_STM32_G0B1XB/board/board.c
Normal file
266
platforms/chibios/boards/GENERIC_STM32_G0B1XB/board/board.c
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@ -0,0 +1,266 @@
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/*
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* This file has been automatically generated using ChibiStudio board
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* generator plugin. Do not edit manually.
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*/
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#include "hal.h"
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#include "stm32_gpio.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/**
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* @brief Type of STM32 GPIO port setup.
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*/
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typedef struct {
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uint32_t moder;
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uint32_t otyper;
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uint32_t ospeedr;
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uint32_t pupdr;
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uint32_t odr;
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uint32_t afrl;
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uint32_t afrh;
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} gpio_setup_t;
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/**
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* @brief Type of STM32 GPIO initialization data.
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*/
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typedef struct {
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#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
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gpio_setup_t PAData;
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#endif
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#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
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gpio_setup_t PBData;
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#endif
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#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
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gpio_setup_t PCData;
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#endif
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#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
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gpio_setup_t PDData;
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#endif
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#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
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gpio_setup_t PEData;
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#endif
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#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
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gpio_setup_t PFData;
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#endif
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#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
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gpio_setup_t PGData;
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#endif
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#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
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gpio_setup_t PHData;
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#endif
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#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
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gpio_setup_t PIData;
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#endif
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#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
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gpio_setup_t PJData;
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#endif
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#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
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gpio_setup_t PKData;
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#endif
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} gpio_config_t;
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/**
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* @brief STM32 GPIO static initialization data.
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*/
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static const gpio_config_t gpio_default_config = {
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#if STM32_HAS_GPIOA
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{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
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VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
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#endif
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#if STM32_HAS_GPIOB
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{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
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VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
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#endif
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#if STM32_HAS_GPIOC
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{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
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VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
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#endif
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#if STM32_HAS_GPIOD
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{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
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VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
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#endif
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#if STM32_HAS_GPIOE
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{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
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VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
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#endif
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#if STM32_HAS_GPIOF
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{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
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VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
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#endif
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#if STM32_HAS_GPIOG
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{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
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VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
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#endif
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#if STM32_HAS_GPIOH
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{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
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VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
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#endif
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#if STM32_HAS_GPIOI
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{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
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VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
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#endif
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#if STM32_HAS_GPIOJ
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{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
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VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
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#endif
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#if STM32_HAS_GPIOK
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{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
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VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
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#endif
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};
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
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gpiop->OTYPER = config->otyper;
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gpiop->OSPEEDR = config->ospeedr;
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gpiop->PUPDR = config->pupdr;
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gpiop->ODR = config->odr;
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gpiop->AFRL = config->afrl;
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gpiop->AFRH = config->afrh;
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gpiop->MODER = config->moder;
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}
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static void stm32_gpio_init(void) {
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/* Enabling GPIO-related clocks, the mask comes from the
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registry header file.*/
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rccResetIOP(STM32_GPIO_EN_MASK);
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rccEnableIOP(STM32_GPIO_EN_MASK, true);
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/* Initializing all the defined GPIO ports.*/
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#if STM32_HAS_GPIOA
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gpio_init(GPIOA, &gpio_default_config.PAData);
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#endif
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#if STM32_HAS_GPIOB
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gpio_init(GPIOB, &gpio_default_config.PBData);
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#endif
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#if STM32_HAS_GPIOC
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gpio_init(GPIOC, &gpio_default_config.PCData);
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#endif
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#if STM32_HAS_GPIOD
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gpio_init(GPIOD, &gpio_default_config.PDData);
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#endif
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#if STM32_HAS_GPIOE
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gpio_init(GPIOE, &gpio_default_config.PEData);
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#endif
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#if STM32_HAS_GPIOF
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gpio_init(GPIOF, &gpio_default_config.PFData);
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#endif
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#if STM32_HAS_GPIOG
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gpio_init(GPIOG, &gpio_default_config.PGData);
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#endif
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#if STM32_HAS_GPIOH
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gpio_init(GPIOH, &gpio_default_config.PHData);
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#endif
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#if STM32_HAS_GPIOI
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gpio_init(GPIOI, &gpio_default_config.PIData);
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#endif
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#if STM32_HAS_GPIOJ
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gpio_init(GPIOJ, &gpio_default_config.PJData);
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#endif
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#if STM32_HAS_GPIOK
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gpio_init(GPIOK, &gpio_default_config.PKData);
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#endif
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Early initialization code.
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* @details GPIO ports and system clocks are initialized before everything
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* else.
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*/
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void __early_init(void) {
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stm32_gpio_init();
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stm32_clock_init();
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}
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#if HAL_USE_SDC || defined(__DOXYGEN__)
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/**
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* @brief SDC card detection.
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*/
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bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
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(void)sdcp;
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/* CHTODO: Fill the implementation.*/
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return true;
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}
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/**
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* @brief SDC card write protection detection.
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*/
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bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
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(void)sdcp;
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/* CHTODO: Fill the implementation.*/
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return false;
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}
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#endif /* HAL_USE_SDC */
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#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
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/**
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* @brief MMC_SPI card detection.
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*/
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bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
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(void)mmcp;
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/* CHTODO: Fill the implementation.*/
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return true;
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}
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/**
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* @brief MMC_SPI card write protection detection.
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*/
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bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
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(void)mmcp;
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/* CHTODO: Fill the implementation.*/
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return false;
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}
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#endif
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/**
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* @brief Board-specific initialization code.
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* @note Add your board-specific code, if any.
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*/
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void boardInit(void) {
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}
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@ -0,0 +1,9 @@
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# List of all the board related files.
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BOARDSRC = $(BOARD_PATH)/board/board.c
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# Required include directories
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BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G0B1RE
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# Shared variables
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ALLCSRC += $(BOARDSRC)
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ALLINC += $(BOARDINC)
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@ -0,0 +1,7 @@
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// Copyright 2024 Stefan Kerkmann (@karlk90)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
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# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
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#endif
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310
platforms/chibios/boards/GENERIC_STM32_G0B1XB/configs/mcuconf.h
Normal file
310
platforms/chibios/boards/GENERIC_STM32_G0B1XB/configs/mcuconf.h
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@ -0,0 +1,310 @@
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/*
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* STM32G0xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 3...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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#define STM32G0xx_MCUCONF
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#define STM32G0B1_MCUCONF
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#define STM32G0C1_MCUCONF
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/*
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* HAL driver system settings.
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_CLOCK_DYNAMIC TRUE
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#define STM32_VOS STM32_VOS_RANGE1
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#define STM32_PWR_CR2 (STM32_PVDRT_LEV0 | STM32_PVDFT_LEV0 | STM32_PVDE_DISABLED)
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#define STM32_PWR_CR3 (PWR_CR3_EIWUL)
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#define STM32_PWR_CR4 (0U)
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#define STM32_PWR_PUCRA (0U)
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#define STM32_PWR_PDCRA (0U)
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#define STM32_PWR_PUCRB (0U)
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#define STM32_PWR_PDCRB (0U)
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#define STM32_PWR_PUCRC (0U)
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#define STM32_PWR_PDCRC (0U)
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#define STM32_PWR_PUCRD (0U)
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#define STM32_PWR_PDCRD (0U)
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#define STM32_PWR_PUCRE (0U)
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#define STM32_PWR_PDCRE (0U)
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#define STM32_PWR_PUCRF (0U)
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#define STM32_PWR_PDCRF (0U)
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#define STM32_HSIDIV_VALUE 1
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#define STM32_HSI16_ENABLED TRUE
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#define STM32_HSI48_ENABLED TRUE
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#define STM32_HSE_ENABLED FALSE
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#define STM32_LSI_ENABLED FALSE
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#define STM32_LSE_ENABLED FALSE
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#define STM32_SW STM32_SW_PLLRCLK
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#define STM32_PLLSRC STM32_PLLSRC_HSI16
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#define STM32_PLLM_VALUE 2
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#define STM32_PLLN_VALUE 16
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#define STM32_PLLP_VALUE 2
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#define STM32_PLLQ_VALUE 4
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#define STM32_PLLR_VALUE 2
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE STM32_PPRE_DIV1
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#define STM32_MCOPRE STM32_MCOPRE_DIV1
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#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
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/*
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* Peripherals clocks and sources.
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*/
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#define STM32_FDCANSEL STM32_USBSEL_HSI48
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#define STM32_USBSEL STM32_USBSEL_HSI48
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#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
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#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
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#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
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#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
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#define STM32_LPUART2SEL STM32_LPUART2SEL_SYSCLK
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#define STM32_CECSEL STM32_CECSEL_HSI16DIV
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#define STM32_I2C1SEL STM32_I2C1SEL_PCLK
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#define STM32_I2C2SEL STM32_I2C1SEL_PCLK
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#define STM32_I2S1SEL STM32_I2S1SEL_SYSCLK
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#define STM32_I2S2SEL STM32_I2S2SEL_SYSCLK
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#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK
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#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK
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#define STM32_TIM1SEL STM32_TIM1SEL_TIMPCLK
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#define STM32_TIM15SEL STM32_TIM15SEL_TIMPCLK
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#define STM32_RNGSEL STM32_RNGSEL_HSI16
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#define STM32_RNGDIV_VALUE 1
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#define STM32_ADCSEL STM32_ADCSEL_PLLPCLK
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#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
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/*
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* Shared IRQ settings.
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*/
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||||
#define STM32_IRQ_EXTI0_1_PRIORITY 3
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||||
#define STM32_IRQ_EXTI2_3_PRIORITY 3
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#define STM32_IRQ_EXTI4_15_PRIORITY 3
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#define STM32_IRQ_EXTI1921_PRIORITY 3
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#define STM32_IRQ_USART1_PRIORITY 2
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#define STM32_IRQ_USART2_LP2_PRIORITY 2
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#define STM32_IRQ_USART3_4_5_6_LP1_PRIORITY 2
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#define STM32_IRQ_TIM1_UP_PRIORITY 1
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#define STM32_IRQ_TIM1_CC_PRIORITY 1
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#define STM32_IRQ_TIM2_PRIORITY 1
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#define STM32_IRQ_TIM3_4_PRIORITY 1
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#define STM32_IRQ_TIM6_PRIORITY 1
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#define STM32_IRQ_TIM7_PRIORITY 1
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||||
#define STM32_IRQ_TIM14_PRIORITY 1
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||||
#define STM32_IRQ_TIM15_PRIORITY 1
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#define STM32_IRQ_TIM16_PRIORITY 1
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#define STM32_IRQ_TIM17_PRIORITY 1
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/*
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* ADC driver system settings.
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*/
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK
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||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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||||
#define STM32_ADC_PRESCALER_VALUE 2
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/*
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* DAC driver system settings.
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*/
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#define STM32_DAC_DUAL_MODE FALSE
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||||
#define STM32_DAC_USE_DAC1_CH1 FALSE
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||||
#define STM32_DAC_USE_DAC1_CH2 FALSE
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 3
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 3
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 FALSE
|
||||
#define STM32_GPT_USE_TIM2 FALSE
|
||||
#define STM32_GPT_USE_TIM3 FALSE
|
||||
#define STM32_GPT_USE_TIM4 FALSE
|
||||
#define STM32_GPT_USE_TIM6 FALSE
|
||||
#define STM32_GPT_USE_TIM7 FALSE
|
||||
#define STM32_GPT_USE_TIM14 FALSE
|
||||
#define STM32_GPT_USE_TIM15 FALSE
|
||||
#define STM32_GPT_USE_TIM16 FALSE
|
||||
#define STM32_GPT_USE_TIM17 FALSE
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 FALSE
|
||||
#define STM32_I2C_USE_I2C2 FALSE
|
||||
#define STM32_I2C_USE_I2C3 FALSE
|
||||
#define STM32_I2C_BUSY_TIMEOUT 50
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY 3
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY 3
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 3
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 3
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 FALSE
|
||||
#define STM32_ICU_USE_TIM2 FALSE
|
||||
#define STM32_ICU_USE_TIM3 FALSE
|
||||
#define STM32_ICU_USE_TIM4 FALSE
|
||||
#define STM32_ICU_USE_TIM15 FALSE
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_TIM1 FALSE
|
||||
#define STM32_PWM_USE_TIM2 FALSE
|
||||
#define STM32_PWM_USE_TIM3 FALSE
|
||||
#define STM32_PWM_USE_TIM4 FALSE
|
||||
#define STM32_PWM_USE_TIM14 FALSE
|
||||
#define STM32_PWM_USE_TIM15 FALSE
|
||||
#define STM32_PWM_USE_TIM16 FALSE
|
||||
#define STM32_PWM_USE_TIM17 FALSE
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_PRESA_VALUE 32
|
||||
#define STM32_RTC_PRESS_VALUE 1024
|
||||
#define STM32_RTC_CR_INIT 0
|
||||
#define STM32_RTC_TAMPCR_INIT 0
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 FALSE
|
||||
#define STM32_SERIAL_USE_USART2 FALSE
|
||||
#define STM32_SERIAL_USE_USART3 FALSE
|
||||
#define STM32_SERIAL_USE_UART4 FALSE
|
||||
#define STM32_SERIAL_USE_UART5 FALSE
|
||||
#define STM32_SERIAL_USE_USART6 FALSE
|
||||
#define STM32_SERIAL_USE_LPUART1 FALSE
|
||||
#define STM32_SERIAL_USE_LPUART2 FALSE
|
||||
|
||||
/*
|
||||
* SIO driver system settings.
|
||||
*/
|
||||
#define STM32_SIO_USE_USART1 FALSE
|
||||
#define STM32_SIO_USE_USART2 FALSE
|
||||
#define STM32_SIO_USE_USART3 FALSE
|
||||
#define STM32_SIO_USE_UART4 FALSE
|
||||
#define STM32_SIO_USE_UART5 FALSE
|
||||
#define STM32_SIO_USE_USART6 FALSE
|
||||
#define STM32_SIO_USE_LPUART1 FALSE
|
||||
#define STM32_SIO_USE_LPUART2 FALSE
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 FALSE
|
||||
#define STM32_SPI_USE_SPI2 FALSE
|
||||
#define STM32_SPI_USE_SPI3 FALSE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY 2
|
||||
#define STM32_ST_USE_TIMER 2
|
||||
|
||||
/*
|
||||
* TRNG driver system settings.
|
||||
* NOTE: STM32G0C1 only.
|
||||
*/
|
||||
#define STM32_TRNG_USE_RNG1 FALSE
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 FALSE
|
||||
#define STM32_UART_USE_USART2 FALSE
|
||||
#define STM32_UART_USE_USART3 FALSE
|
||||
#define STM32_UART_USE_UART4 FALSE
|
||||
#define STM32_UART_USE_UART5 FALSE
|
||||
#define STM32_UART_USE_USART6 FALSE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||||
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_USB1 TRUE
|
||||
#define STM32_USB_USB1_LP_IRQ_PRIORITY 3
|
||||
#define STM32_USB_USE_ISOCHRONOUS FALSE
|
||||
#define STM32_USB_USE_FAST_COPY TRUE
|
||||
#define STM32_USB_HOST_WAKEUP_DURATION 2
|
||||
#define STM32_USB_48MHZ_DELTA 0
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG FALSE
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
85
platforms/chibios/boards/common/ld/STM32G0B1xB.ld
Normal file
85
platforms/chibios/boards/common/ld/STM32G0B1xB.ld
Normal file
@ -0,0 +1,85 @@
|
||||
/*
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* STM32G0B1xB memory setup.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash0 (rx) : org = 0x08000000, len = 128k
|
||||
flash1 (rx) : org = 0x00000000, len = 0
|
||||
flash2 (rx) : org = 0x00000000, len = 0
|
||||
flash3 (rx) : org = 0x00000000, len = 0
|
||||
flash4 (rx) : org = 0x00000000, len = 0
|
||||
flash5 (rx) : org = 0x00000000, len = 0
|
||||
flash6 (rx) : org = 0x00000000, len = 0
|
||||
flash7 (rx) : org = 0x00000000, len = 0
|
||||
ram0 (wx) : org = 0x20000000, len = 144k
|
||||
ram1 (wx) : org = 0x00000000, len = 0
|
||||
ram2 (wx) : org = 0x00000000, len = 0
|
||||
ram3 (wx) : org = 0x00000000, len = 0
|
||||
ram4 (wx) : org = 0x00000000, len = 0
|
||||
ram5 (wx) : org = 0x00000000, len = 0
|
||||
ram6 (wx) : org = 0x00000000, len = 0
|
||||
ram7 (wx) : org = 0x00000000, len = 0
|
||||
}
|
||||
|
||||
/* For each data/text section two region are defined, a virtual region
|
||||
and a load region (_LMA suffix).*/
|
||||
|
||||
/* Flash region to be used for exception vectors.*/
|
||||
REGION_ALIAS("VECTORS_FLASH", flash0);
|
||||
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for constructors and destructors.*/
|
||||
REGION_ALIAS("XTORS_FLASH", flash0);
|
||||
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for code text.*/
|
||||
REGION_ALIAS("TEXT_FLASH", flash0);
|
||||
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for read only data.*/
|
||||
REGION_ALIAS("RODATA_FLASH", flash0);
|
||||
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for various.*/
|
||||
REGION_ALIAS("VARIOUS_FLASH", flash0);
|
||||
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for RAM(n) initialization data.*/
|
||||
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
|
||||
|
||||
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||
of all exceptions and interrupts.*/
|
||||
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||
|
||||
/* RAM region to be used for the process stack. This is the stack used by
|
||||
the main() function.*/
|
||||
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||
|
||||
/* RAM region to be used for data segment.*/
|
||||
REGION_ALIAS("DATA_RAM", ram0);
|
||||
REGION_ALIAS("DATA_RAM_LMA", flash0);
|
||||
|
||||
/* RAM region to be used for BSS segment.*/
|
||||
REGION_ALIAS("BSS_RAM", ram0);
|
||||
|
||||
/* RAM region to be used for the default heap.*/
|
||||
REGION_ALIAS("HEAP_RAM", ram0);
|
||||
|
||||
/* Generic rules inclusion.*/
|
||||
INCLUDE rules.ld
|
||||
Loading…
Reference in New Issue
Block a user