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Co-authored-by: Sergey Vlasov <sigprof@gmail.com>
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Drashna Jaelre 2024-09-20 18:50:42 -07:00 committed by GitHub
parent 65363c6102
commit c4bbe41e0d
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GPG Key ID: B5690EEEBB952194
4 changed files with 4 additions and 4 deletions
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2
platforms/chibios/boards/common/ld/STM32F446xE.ld
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@ -8,6 +8,6 @@ f4xx_flash_size = 512k;
f4xx_ram1_size = 112k; f4xx_ram1_size = 112k;
f4xx_ram2_size = 16k; f4xx_ram2_size = 16k;
f4xx_ram4_size = 0; f4xx_ram4_size = 0;
f4xx_ram5_size = 0; f4xx_ram5_size = 4k;
INCLUDE stm32f4xx_common.ld INCLUDE stm32f4xx_common.ld

2
platforms/chibios/boards/common/ld/STM32F446xE_tinyuf2.ld
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@ -8,6 +8,6 @@ f4xx_flash_size = 512k;
f4xx_ram1_size = 112k; f4xx_ram1_size = 112k;
f4xx_ram2_size = 16k; f4xx_ram2_size = 16k;
f4xx_ram4_size = 0; f4xx_ram4_size = 0;
f4xx_ram5_size = 0; f4xx_ram5_size = 4k;
INCLUDE stm32f4xx_tinyuf2_common.ld INCLUDE stm32f4xx_tinyuf2_common.ld

2
platforms/chibios/boards/common/ld/stm32f4xx_common.ld
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@ -26,7 +26,7 @@ MEMORY
flash7 (rx) : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = f4xx_ram1_size + f4xx_ram2_size /* SRAM1 + SRAM2 */ ram0 (wx) : org = 0x20000000, len = f4xx_ram1_size + f4xx_ram2_size /* SRAM1 + SRAM2 */
ram1 (wx) : org = 0x20000000, len = f4xx_ram1_size /* SRAM1 */ ram1 (wx) : org = 0x20000000, len = f4xx_ram1_size /* SRAM1 */
ram2 (wx) : org = 0x2001C000, len = f4xx_ram2_size /* SRAM2 */ ram2 (wx) : org = 0x20000000 + f4xx_ram1_size, len = f4xx_ram2_size /* SRAM2 */
ram3 (wx) : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x10000000, len = f4xx_ram4_size /* CCM SRAM */ ram4 (wx) : org = 0x10000000, len = f4xx_ram4_size /* CCM SRAM */
ram5 (wx) : org = 0x40024000, len = f4xx_ram5_size /* BCKP SRAM */ ram5 (wx) : org = 0x40024000, len = f4xx_ram5_size /* BCKP SRAM */

2
platforms/chibios/boards/common/ld/stm32f4xx_tinyuf2_common.ld
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@ -29,7 +29,7 @@ MEMORY
flash7 (rx) : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = f4xx_ram1_size + f4xx_ram2_size /* SRAM1 + SRAM2 */ ram0 (wx) : org = 0x20000000, len = f4xx_ram1_size + f4xx_ram2_size /* SRAM1 + SRAM2 */
ram1 (wx) : org = 0x20000000, len = f4xx_ram1_size /* SRAM1 */ ram1 (wx) : org = 0x20000000, len = f4xx_ram1_size /* SRAM1 */
ram2 (wx) : org = 0x2001C000, len = f4xx_ram2_size /* SRAM2 */ ram2 (wx) : org = 0x20000000 + f4xx_ram1_size, len = f4xx_ram2_size /* SRAM2 */
ram3 (wx) : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x10000000, len = f4xx_ram4_size /* CCM SRAM */ ram4 (wx) : org = 0x10000000, len = f4xx_ram4_size /* CCM SRAM */
ram5 (wx) : org = 0x40024000, len = f4xx_ram5_size /* BCKP SRAM */ ram5 (wx) : org = 0x40024000, len = f4xx_ram5_size /* BCKP SRAM */