diff --git a/builddefs/common_features.mk b/builddefs/common_features.mk index c122afcff9b..678b4cdcdc3 100644 --- a/builddefs/common_features.mk +++ b/builddefs/common_features.mk @@ -221,7 +221,7 @@ ifneq ($(strip $(EEPROM_DRIVER)),none) COMMON_VPATH += $(PLATFORM_PATH)/$(PLATFORM_KEY)/$(DRIVER_DIR)/flash COMMON_VPATH += $(DRIVER_PATH)/flash SRC += eeprom_driver.c eeprom_legacy_emulated_flash.c legacy_flash_ops.c - else ifneq ($(filter $(MCU_SERIES),STM32F1xx STM32F3xx STM32F4xx STM32L4xx STM32G0xx STM32G4xx WB32F3G71xx WB32FQ95xx AT32F415 GD32VF103),) + else ifneq ($(filter $(MCU_SERIES),STM32F1xx STM32F3xx STM32F4xx STM32L4xx STM32G0xx STM32G4xx WB32F3G71xx WB32FQ95xx AT32F402_405 AT32F415 GD32VF103),) # Wear-leveling EEPROM implementation, backed by MCU flash OPT_DEFS += -DEEPROM_DRIVER -DEEPROM_WEAR_LEVELING SRC += eeprom_driver.c eeprom_wear_leveling.c @@ -984,6 +984,7 @@ ifeq ($(strip $(WS2812_DRIVER_REQUIRED)), yes) ifeq ($(strip $(PLATFORM)), CHIBIOS) ifeq ($(strip $(WS2812_DRIVER)), pwm) OPT_DEFS += -DSTM32_DMA_REQUIRED=TRUE + OPT_DEFS += -DAT32_DMA_REQUIRED=TRUE endif endif diff --git a/data/schemas/keyboard.jsonschema b/data/schemas/keyboard.jsonschema index 13ceec5afab..fb63dd1ba36 100644 --- a/data/schemas/keyboard.jsonschema +++ b/data/schemas/keyboard.jsonschema @@ -98,6 +98,8 @@ "GD32VF103", "WB32F3G71", "WB32FQ95", + "AT32F402", + "AT32F405", "AT32F415", "atmega16u2", "atmega32u2", diff --git a/docs/compatible_microcontrollers.md b/docs/compatible_microcontrollers.md index f148c39191e..1b5299a9507 100644 --- a/docs/compatible_microcontrollers.md +++ b/docs/compatible_microcontrollers.md @@ -59,6 +59,8 @@ You can also use any ARM chip with USB that [ChibiOS](https://www.chibios.org) s ### Artery (AT32) + * [AT32F402](https://www.arterychip.com/en/product/AT32F402.jsp) + * [AT32F405](https://www.arterychip.com/en/product/AT32F405.jsp) * [AT32F415](https://www.arterychip.com/en/product/AT32F415.jsp) ### NXP (Kinetis) diff --git a/keyboards/handwired/onekey/at_start_f402/board.h b/keyboards/handwired/onekey/at_start_f402/board.h new file mode 100644 index 00000000000..6ec6c065fbb --- /dev/null +++ b/keyboards/handwired/onekey/at_start_f402/board.h @@ -0,0 +1,13 @@ +// Copyright 2023-2025 HorrorTroll +// Copyright 2023-2025 Zhaqian +// SPDX-License-Identifier: GPL-2.0-or-later + +#pragma once + +#include_next + +#undef AT32F402KB +#define AT32F402RC + +#undef AT32_HEXTCLK +#define AT32_HEXTCLK 12000000 diff --git a/keyboards/handwired/onekey/at_start_f402/config.h b/keyboards/handwired/onekey/at_start_f402/config.h new file mode 100644 index 00000000000..ca276782951 --- /dev/null +++ b/keyboards/handwired/onekey/at_start_f402/config.h @@ -0,0 +1,21 @@ +// Copyright 2023-2025 HorrorTroll +// Copyright 2023-2025 Zhaqian +// SPDX-License-Identifier: GPL-2.0-or-later + +#pragma once + +#define ADC_PIN A0 + +#define BACKLIGHT_PWM_DRIVER PWMD3 +#define BACKLIGHT_PWM_CHANNEL 2 + +/* I2C 400 kHz speed */ +#define I2C1_TIMINGR_PRESC 2U +#define I2C1_TIMINGR_SCLDEL 12U +#define I2C1_TIMINGR_SDADEL 0U +#define I2C1_TIMINGR_SCLH 29U +#define I2C1_TIMINGR_SCLL 52U + +#define SOLENOID_PIN B12 +#define SOLENOID_PINS { B12, B13, B14, B15 } +#define SOLENOID_PINS_ACTIVE_STATE { high, high, low } diff --git a/keyboards/handwired/onekey/at_start_f402/halconf.h b/keyboards/handwired/onekey/at_start_f402/halconf.h new file mode 100644 index 00000000000..e3c075936dc --- /dev/null +++ b/keyboards/handwired/onekey/at_start_f402/halconf.h @@ -0,0 +1,13 @@ +// Copyright 2023-2025 HorrorTroll +// Copyright 2023-2025 Zhaqian +// SPDX-License-Identifier: GPL-2.0-or-later + +#pragma once + +#define HAL_USE_ADC TRUE + +#define HAL_USE_I2C TRUE + +#define HAL_USE_PWM TRUE + +#include_next diff --git a/keyboards/handwired/onekey/at_start_f402/keyboard.json b/keyboards/handwired/onekey/at_start_f402/keyboard.json new file mode 100644 index 00000000000..22edac38224 --- /dev/null +++ b/keyboards/handwired/onekey/at_start_f402/keyboard.json @@ -0,0 +1,19 @@ +{ + "keyboard_name": "Onekey AT-START-F402", + "processor": "AT32F402", + "bootloader": "at32-dfu", + "matrix_pins": { + "cols": ["B3"], + "rows": ["B4"] + }, + "backlight": { + "pin": "B5" + }, + "ws2812": { + "pin": "B0" + }, + "apa102": { + "data_pin": "B0", + "clock_pin": "B1" + } +} diff --git a/keyboards/handwired/onekey/at_start_f402/mcuconf.h b/keyboards/handwired/onekey/at_start_f402/mcuconf.h new file mode 100644 index 00000000000..ead32d82f39 --- /dev/null +++ b/keyboards/handwired/onekey/at_start_f402/mcuconf.h @@ -0,0 +1,19 @@ +// Copyright 2023-2025 HorrorTroll +// Copyright 2023-2025 Zhaqian +// SPDX-License-Identifier: GPL-2.0-or-later + +#pragma once + +#include_next + +#undef AT32_PLL_NS_VALUE +#define AT32_PLL_NS_VALUE 72 + +#undef AT32_ADC_USE_ADC1 +#define AT32_ADC_USE_ADC1 TRUE + +#undef AT32_I2C_USE_I2C1 +#define AT32_I2C_USE_I2C1 TRUE + +#undef AT32_PWM_USE_TMR3 +#define AT32_PWM_USE_TMR3 TRUE diff --git a/keyboards/handwired/onekey/at_start_f402/readme.md b/keyboards/handwired/onekey/at_start_f402/readme.md new file mode 100644 index 00000000000..337bdb0be9e --- /dev/null +++ b/keyboards/handwired/onekey/at_start_f402/readme.md @@ -0,0 +1,3 @@ +# Artery AT-START-F402 Board Onekey + +To trigger keypress, short together pins *B3* and *B4*. diff --git a/keyboards/handwired/onekey/at_start_f402/rules.mk b/keyboards/handwired/onekey/at_start_f402/rules.mk new file mode 100644 index 00000000000..6d8bef3f244 --- /dev/null +++ b/keyboards/handwired/onekey/at_start_f402/rules.mk @@ -0,0 +1 @@ +MCU_LDSCRIPT = AT32F402xC diff --git a/keyboards/handwired/onekey/at_start_f405/board.h b/keyboards/handwired/onekey/at_start_f405/board.h new file mode 100644 index 00000000000..c8956b65a47 --- /dev/null +++ b/keyboards/handwired/onekey/at_start_f405/board.h @@ -0,0 +1,10 @@ +// Copyright 2023-2025 HorrorTroll +// Copyright 2023-2025 Zhaqian +// SPDX-License-Identifier: GPL-2.0-or-later + +#pragma once + +#include_next + +#undef AT32F405KB +#define AT32F405RC diff --git a/keyboards/handwired/onekey/at_start_f405/config.h b/keyboards/handwired/onekey/at_start_f405/config.h new file mode 100644 index 00000000000..ca276782951 --- /dev/null +++ b/keyboards/handwired/onekey/at_start_f405/config.h @@ -0,0 +1,21 @@ +// Copyright 2023-2025 HorrorTroll +// Copyright 2023-2025 Zhaqian +// SPDX-License-Identifier: GPL-2.0-or-later + +#pragma once + +#define ADC_PIN A0 + +#define BACKLIGHT_PWM_DRIVER PWMD3 +#define BACKLIGHT_PWM_CHANNEL 2 + +/* I2C 400 kHz speed */ +#define I2C1_TIMINGR_PRESC 2U +#define I2C1_TIMINGR_SCLDEL 12U +#define I2C1_TIMINGR_SDADEL 0U +#define I2C1_TIMINGR_SCLH 29U +#define I2C1_TIMINGR_SCLL 52U + +#define SOLENOID_PIN B12 +#define SOLENOID_PINS { B12, B13, B14, B15 } +#define SOLENOID_PINS_ACTIVE_STATE { high, high, low } diff --git a/keyboards/handwired/onekey/at_start_f405/halconf.h b/keyboards/handwired/onekey/at_start_f405/halconf.h new file mode 100644 index 00000000000..e3c075936dc --- /dev/null +++ b/keyboards/handwired/onekey/at_start_f405/halconf.h @@ -0,0 +1,13 @@ +// Copyright 2023-2025 HorrorTroll +// Copyright 2023-2025 Zhaqian +// SPDX-License-Identifier: GPL-2.0-or-later + +#pragma once + +#define HAL_USE_ADC TRUE + +#define HAL_USE_I2C TRUE + +#define HAL_USE_PWM TRUE + +#include_next diff --git a/keyboards/handwired/onekey/at_start_f405/keyboard.json b/keyboards/handwired/onekey/at_start_f405/keyboard.json new file mode 100644 index 00000000000..e0ff8c33089 --- /dev/null +++ b/keyboards/handwired/onekey/at_start_f405/keyboard.json @@ -0,0 +1,19 @@ +{ + "keyboard_name": "Onekey AT-START-F405", + "processor": "AT32F405", + "bootloader": "at32-dfu", + "matrix_pins": { + "cols": ["B3"], + "rows": ["B4"] + }, + "backlight": { + "pin": "B5" + }, + "ws2812": { + "pin": "B0" + }, + "apa102": { + "data_pin": "B0", + "clock_pin": "B1" + } +} diff --git a/keyboards/handwired/onekey/at_start_f405/mcuconf.h b/keyboards/handwired/onekey/at_start_f405/mcuconf.h new file mode 100644 index 00000000000..642d98d7fc3 --- /dev/null +++ b/keyboards/handwired/onekey/at_start_f405/mcuconf.h @@ -0,0 +1,16 @@ +// Copyright 2023-2025 HorrorTroll +// Copyright 2023-2025 Zhaqian +// SPDX-License-Identifier: GPL-2.0-or-later + +#pragma once + +#include_next + +#undef AT32_ADC_USE_ADC1 +#define AT32_ADC_USE_ADC1 TRUE + +#undef AT32_I2C_USE_I2C1 +#define AT32_I2C_USE_I2C1 TRUE + +#undef AT32_PWM_USE_TMR3 +#define AT32_PWM_USE_TMR3 TRUE diff --git a/keyboards/handwired/onekey/at_start_f405/readme.md b/keyboards/handwired/onekey/at_start_f405/readme.md new file mode 100644 index 00000000000..f2d2a5028be --- /dev/null +++ b/keyboards/handwired/onekey/at_start_f405/readme.md @@ -0,0 +1,3 @@ +# Artery AT-START-F405 Board Onekey + +To trigger keypress, short together pins *B3* and *B4*. diff --git a/keyboards/handwired/onekey/at_start_f405/rules.mk b/keyboards/handwired/onekey/at_start_f405/rules.mk new file mode 100644 index 00000000000..2700e607553 --- /dev/null +++ b/keyboards/handwired/onekey/at_start_f405/rules.mk @@ -0,0 +1 @@ +MCU_LDSCRIPT = AT32F405xC diff --git a/lib/python/qmk/constants.py b/lib/python/qmk/constants.py index e3e47c2bd28..b1c6e0d2cd5 100644 --- a/lib/python/qmk/constants.py +++ b/lib/python/qmk/constants.py @@ -22,7 +22,7 @@ QMK_FIRMWARE_UPSTREAM = 'qmk/qmk_firmware' MAX_KEYBOARD_SUBFOLDERS = 5 # Supported processor types -CHIBIOS_PROCESSORS = 'cortex-m0', 'cortex-m0plus', 'cortex-m3', 'cortex-m4', 'MKL26Z64', 'MK20DX128', 'MK20DX256', 'MK64FX512', 'MK66FX1M0', 'RP2040', 'STM32F042', 'STM32F072', 'STM32F103', 'STM32F303', 'STM32F401', 'STM32F405', 'STM32F407', 'STM32F411', 'STM32F446', 'STM32G0B1', 'STM32G431', 'STM32G474', 'STM32H723', 'STM32H733', 'STM32L412', 'STM32L422', 'STM32L432', 'STM32L433', 'STM32L442', 'STM32L443', 'GD32VF103', 'WB32F3G71', 'WB32FQ95', 'AT32F415' +CHIBIOS_PROCESSORS = 'cortex-m0', 'cortex-m0plus', 'cortex-m3', 'cortex-m4', 'MKL26Z64', 'MK20DX128', 'MK20DX256', 'MK64FX512', 'MK66FX1M0', 'RP2040', 'STM32F042', 'STM32F072', 'STM32F103', 'STM32F303', 'STM32F401', 'STM32F405', 'STM32F407', 'STM32F411', 'STM32F446', 'STM32G0B1', 'STM32G431', 'STM32G474', 'STM32H723', 'STM32H733', 'STM32L412', 'STM32L422', 'STM32L432', 'STM32L433', 'STM32L442', 'STM32L443', 'GD32VF103', 'WB32F3G71', 'WB32FQ95', 'AT32F402', 'AT32F405', 'AT32F415' LUFA_PROCESSORS = 'at90usb162', 'atmega16u2', 'atmega32u2', 'atmega16u4', 'atmega32u4', 'at90usb646', 'at90usb647', 'at90usb1286', 'at90usb1287', None VUSB_PROCESSORS = 'atmega32a', 'atmega328p', 'atmega328', 'attiny85' @@ -56,6 +56,8 @@ MCU2BOOTLOADER = { "GD32VF103": "gd32v-dfu", "WB32F3G71": "wb32-dfu", "WB32FQ95": "wb32-dfu", + "AT32F402": "at32-dfu", + "AT32F405": "at32-dfu", "AT32F415": "at32-dfu", "atmega16u2": "atmel-dfu", "atmega32u2": "atmel-dfu", diff --git a/platforms/chibios/boards/GENERIC_AT32_F402XX/board/board.c b/platforms/chibios/boards/GENERIC_AT32_F402XX/board/board.c new file mode 100644 index 00000000000..bce33e714d5 --- /dev/null +++ b/platforms/chibios/boards/GENERIC_AT32_F402XX/board/board.c @@ -0,0 +1,158 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" +#include "at32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of AT32 GPIO port setup. + */ +typedef struct { + uint32_t cfgr; + uint32_t omode; + uint32_t odrvr; + uint32_t pull; + uint32_t odt; + uint32_t muxl; + uint32_t muxh; + uint32_t hdrv; +} gpio_setup_t; + +/** + * @brief Type of AT32 GPIO initialization data. + */ +typedef struct { +#if AT32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if AT32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if AT32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if AT32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if AT32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +} gpio_config_t; + +/** + * @brief AT32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if AT32_HAS_GPIOA + {VAL_GPIOA_CFGR, VAL_GPIOA_OMODE, VAL_GPIOA_ODRVR, VAL_GPIOA_PULL, + VAL_GPIOA_ODT, VAL_GPIOA_MUXL, VAL_GPIOA_MUXH, VAL_GPIOA_HDRV}, +#endif +#if AT32_HAS_GPIOB + {VAL_GPIOB_CFGR, VAL_GPIOB_OMODE, VAL_GPIOB_ODRVR, VAL_GPIOB_PULL, + VAL_GPIOB_ODT, VAL_GPIOB_MUXL, VAL_GPIOB_MUXH, VAL_GPIOB_HDRV}, +#endif +#if AT32_HAS_GPIOC + {VAL_GPIOC_CFGR, VAL_GPIOC_OMODE, VAL_GPIOC_ODRVR, VAL_GPIOC_PULL, + VAL_GPIOC_ODT, VAL_GPIOC_MUXL, VAL_GPIOC_MUXH, VAL_GPIOC_HDRV}, +#endif +#if AT32_HAS_GPIOD + {VAL_GPIOD_CFGR, VAL_GPIOD_OMODE, VAL_GPIOD_ODRVR, VAL_GPIOD_PULL, + VAL_GPIOD_ODT, VAL_GPIOD_MUXL, VAL_GPIOD_MUXH, VAL_GPIOD_HDRV}, +#endif +#if AT32_HAS_GPIOF + {VAL_GPIOF_CFGR, VAL_GPIOF_OMODE, VAL_GPIOF_ODRVR, VAL_GPIOF_PULL, + VAL_GPIOF_ODT, VAL_GPIOF_MUXL, VAL_GPIOF_MUXH, VAL_GPIOF_HDRV}, +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(at32_gpio_t *gpiop, const gpio_setup_t *config) { + gpiop->OMODE = config->omode; + gpiop->ODRVR = config->odrvr; + gpiop->PULL = config->pull; + gpiop->ODT = config->odt; + gpiop->MUXL = config->muxl; + gpiop->MUXH = config->muxh; + gpiop->HDRV = config->hdrv; + gpiop->CFGR = config->cfgr; +} + +static void at32_gpio_init(void) { + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + crmResetAHB1(AT32_GPIO_EN_MASK); + crmEnableAHB1(AT32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if AT32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if AT32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if AT32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if AT32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if AT32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + at32_gpio_init(); + at32_clock_init(); +} + +/** + * @brief Board-specific initialization code. + * @note You can add your board-specific code here. + */ +void boardInit(void) { + +} diff --git a/platforms/chibios/boards/GENERIC_AT32_F402XX/board/board.h b/platforms/chibios/boards/GENERIC_AT32_F402XX/board/board.h new file mode 100644 index 00000000000..6ff2e11ac55 --- /dev/null +++ b/platforms/chibios/boards/GENERIC_AT32_F402XX/board/board.h @@ -0,0 +1,654 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * Setup for a Generic AT32F402 board. + */ + +/* + * Board identifier. + */ +#define BOARD_GENERIC_AT32_F402XX +#define BOARD_NAME "GENERIC AT32F402 board" + +/* + * Board oscillators-related settings. + */ +#if !defined(AT32_LEXTCLK) +#define AT32_LEXTCLK 32768 +#endif + +#if !defined(AT32_HEXTCLK) +#define AT32_HEXTCLK 8000000 +#endif + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define AT32F402KB + +/* + * GPIO settings, allow unused GPIO for smaller chip packages. + */ +#if defined(AT32F402KB) || defined(AT32F402KC) +#define AT32_HAS_GPIOC TRUE +#define AT32_HAS_GPIOD TRUE +#elif defined(AT32F402CB) || defined(AT32F402CC) +#define AT32_HAS_GPIOD TRUE +#endif + +/* + * IO pins assignments. + */ +#define GPIOA_PIN0 0U +#define GPIOA_PIN1 1U +#define GPIOA_PIN2 2U +#define GPIOA_PIN3 3U +#define GPIOA_PIN4 4U +#define GPIOA_PIN5 5U +#define GPIOA_PIN6 6U +#define GPIOA_PIN7 7U +#define GPIOA_PIN8 8U +#define GPIOA_PIN9 9U +#define GPIOA_PIN10 10U +#define GPIOA_PIN11 11U +#define GPIOA_PIN12 12U +#define GPIOA_PIN13 13U +#define GPIOA_PIN14 14U +#define GPIOA_PIN15 15U + +#define GPIOB_PIN0 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_PIN3 3U +#define GPIOB_PIN4 4U +#define GPIOB_PIN5 5U +#define GPIOB_PIN6 6U +#define GPIOB_PIN7 7U +#define GPIOB_PIN8 8U +#define GPIOB_PIN9 9U +#define GPIOB_PIN10 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_PIN13 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U + +#define GPIOC_PIN0 0U +#define GPIOC_PIN1 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_PIN7 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_PIN14 14U +#define GPIOC_PIN15 15U + +#define GPIOD_PIN2 2U + +#define GPIOF_HEXT_IN 0U +#define GPIOF_HEXT_OUT 1U +#define GPIOF_PIN4 4U +#define GPIOF_PIN5 5U +#define GPIOF_PIN6 6U +#define GPIOF_PIN7 7U +#define GPIOF_PIN11 11U + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the AT32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_MUX(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODT_LOW(n) (0U << (n)) +#define PIN_ODT_HIGH(n) (1U << (n)) +#define PIN_OMODE_PUSHPULL(n) (0U << (n)) +#define PIN_OMODE_OPENDRAIN(n) (1U << (n)) +#define PIN_ODRVR_STRONGER(n) (1U << ((n) * 2U)) +#define PIN_ODRVR_MODERATE(n) (3U << ((n) * 2U)) +#define PIN_PULL_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PULL_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PULL_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_IOMUX_MUX(n, v) ((v) << (((n) % 8U) * 4U)) +#define PIN_WPR_DISABLED(n) (0U << (n)) +#define PIN_WPR_ENABLED(n) (1U << (n)) +#define PIN_HDRV_DISABLED(n) (0U << (n)) +#define PIN_HDRV_ENABLED(n) (1U << (n)) + +/* + * Port A setup. + * + * PA0 - PIN0 (input pullup). + * PA1 - PIN1 (input pullup). + * PA2 - PIN2 (input pullup). + * PA3 - PIN3 (input pullup). + * PA4 - PIN4 (input pullup). + * PA5 - PIN5 (input pullup). + * PA6 - PIN6 (input pullup). + * PA7 - PIN7 (input pullup). + * PA8 - PIN8 (input pullup). + * PA9 - PIN9 (input pullup). + * PA10 - PIN10 (input pullup). + * PA11 - PIN11 (input floating). + * PA12 - PIN12 (input floating). + * PA13 - PIN13 (input pullup). + * PA14 - PIN14 (input pullup). + * PA15 - PIN15 (input pullup). + */ +#define VAL_GPIOA_CFGR (PIN_MODE_INPUT(GPIOA_PIN0) | \ + PIN_MODE_INPUT(GPIOA_PIN1) | \ + PIN_MODE_INPUT(GPIOA_PIN2) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_INPUT(GPIOA_PIN4) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_INPUT(GPIOA_PIN6) | \ + PIN_MODE_INPUT(GPIOA_PIN7) | \ + PIN_MODE_INPUT(GPIOA_PIN8) | \ + PIN_MODE_INPUT(GPIOA_PIN9) | \ + PIN_MODE_INPUT(GPIOA_PIN10) | \ + PIN_MODE_INPUT(GPIOA_PIN11) | \ + PIN_MODE_INPUT(GPIOA_PIN12) | \ + PIN_MODE_INPUT(GPIOA_PIN13) | \ + PIN_MODE_INPUT(GPIOA_PIN14) | \ + PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_OMODE (PIN_OMODE_PUSHPULL(GPIOA_PIN0) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN1) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN2) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN3) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN4) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN5) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN6) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN7) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN8) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN9) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN10) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN11) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN12) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN13) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN14) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_ODRVR (PIN_ODRVR_STRONGER(GPIOA_PIN0) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN1) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN2) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN3) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN4) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN5) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN6) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN7) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN8) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN9) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN10) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN11) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN12) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN13) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN14) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN15)) +#define VAL_GPIOA_PULL (PIN_PULL_PULLUP(GPIOA_PIN0) | \ + PIN_PULL_PULLUP(GPIOA_PIN1) | \ + PIN_PULL_PULLUP(GPIOA_PIN2) | \ + PIN_PULL_PULLUP(GPIOA_PIN3) | \ + PIN_PULL_PULLUP(GPIOA_PIN4) | \ + PIN_PULL_PULLUP(GPIOA_PIN5) | \ + PIN_PULL_PULLUP(GPIOA_PIN6) | \ + PIN_PULL_PULLUP(GPIOA_PIN7) | \ + PIN_PULL_PULLUP(GPIOA_PIN8) | \ + PIN_PULL_PULLUP(GPIOA_PIN9) | \ + PIN_PULL_PULLUP(GPIOA_PIN10) | \ + PIN_PULL_FLOATING(GPIOA_PIN11) | \ + PIN_PULL_FLOATING(GPIOA_PIN12) | \ + PIN_PULL_PULLUP(GPIOA_PIN13) | \ + PIN_PULL_PULLUP(GPIOA_PIN14) | \ + PIN_PULL_PULLUP(GPIOA_PIN15)) +#define VAL_GPIOA_ODT (PIN_ODT_HIGH(GPIOA_PIN0) | \ + PIN_ODT_HIGH(GPIOA_PIN1) | \ + PIN_ODT_HIGH(GPIOA_PIN2) | \ + PIN_ODT_HIGH(GPIOA_PIN3) | \ + PIN_ODT_HIGH(GPIOA_PIN4) | \ + PIN_ODT_HIGH(GPIOA_PIN5) | \ + PIN_ODT_HIGH(GPIOA_PIN6) | \ + PIN_ODT_HIGH(GPIOA_PIN7) | \ + PIN_ODT_HIGH(GPIOA_PIN8) | \ + PIN_ODT_HIGH(GPIOA_PIN9) | \ + PIN_ODT_HIGH(GPIOA_PIN10) | \ + PIN_ODT_HIGH(GPIOA_PIN11) | \ + PIN_ODT_HIGH(GPIOA_PIN12) | \ + PIN_ODT_HIGH(GPIOA_PIN13) | \ + PIN_ODT_HIGH(GPIOA_PIN14) | \ + PIN_ODT_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_MUXL (PIN_IOMUX_MUX(GPIOA_PIN0, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN1, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN2, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN3, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN4, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN5, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN6, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN7, 0U)) +#define VAL_GPIOA_MUXH (PIN_IOMUX_MUX(GPIOA_PIN8, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN9, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN10, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN11, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN12, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN13, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN14, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN15, 0U)) +#define VAL_GPIOA_HDRV (PIN_HDRV_DISABLED(GPIOA_PIN0) | \ + PIN_HDRV_DISABLED(GPIOA_PIN1) | \ + PIN_HDRV_DISABLED(GPIOA_PIN2) | \ + PIN_HDRV_DISABLED(GPIOA_PIN3) | \ + PIN_HDRV_DISABLED(GPIOA_PIN4) | \ + PIN_HDRV_DISABLED(GPIOA_PIN5) | \ + PIN_HDRV_DISABLED(GPIOA_PIN6) | \ + PIN_HDRV_DISABLED(GPIOA_PIN7) | \ + PIN_HDRV_DISABLED(GPIOA_PIN8) | \ + PIN_HDRV_DISABLED(GPIOA_PIN9) | \ + PIN_HDRV_DISABLED(GPIOA_PIN10) | \ + PIN_HDRV_DISABLED(GPIOA_PIN11) | \ + PIN_HDRV_DISABLED(GPIOA_PIN12) | \ + PIN_HDRV_DISABLED(GPIOA_PIN13) | \ + PIN_HDRV_DISABLED(GPIOA_PIN14) | \ + PIN_HDRV_DISABLED(GPIOA_PIN15)) + +/* + * Port B setup. + * + * PB0 - PIN0 (input pullup). + * PB1 - PIN1 (input pullup). + * PB2 - PIN2 (input pullup). + * PB3 - PIN3 (input pullup). + * PB4 - PIN4 (input pullup). + * PB5 - PIN5 (input pullup). + * PB6 - PIN6 (input pullup). + * PB7 - PIN7 (input pullup). + * PB8 - PIN8 (input pullup). + * PB9 - PIN9 (input pullup). + * PB10 - PIN10 (input pullup). + * PB11 - PIN11 (input pullup). + * PB12 - PIN12 (input pullup). + * PB13 - PIN13 (input pullup). + * PB14 - PIN14 (input pullup). + * PB15 - PIN15 (input pullup). + */ +#define VAL_GPIOB_CFGR (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_INPUT(GPIOB_PIN3) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_INPUT(GPIOB_PIN6) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_INPUT(GPIOB_PIN9) | \ + PIN_MODE_INPUT(GPIOB_PIN10) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_INPUT(GPIOB_PIN13) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_OMODE (PIN_OMODE_PUSHPULL(GPIOB_PIN0) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN3) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN4) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN6) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN8) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN9) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN10) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN13) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_ODRVR (PIN_ODRVR_STRONGER(GPIOB_PIN0) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN1) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN2) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN3) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN4) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN5) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN6) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN7) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN8) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN9) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN10) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN11) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN12) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN13) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN14) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN15)) +#define VAL_GPIOB_PULL (PIN_PULL_PULLUP(GPIOB_PIN0) | \ + PIN_PULL_PULLUP(GPIOB_PIN1) | \ + PIN_PULL_PULLUP(GPIOB_PIN2) | \ + PIN_PULL_PULLUP(GPIOB_PIN3) | \ + PIN_PULL_PULLUP(GPIOB_PIN4) | \ + PIN_PULL_PULLUP(GPIOB_PIN5) | \ + PIN_PULL_PULLUP(GPIOB_PIN6) | \ + PIN_PULL_PULLUP(GPIOB_PIN7) | \ + PIN_PULL_PULLUP(GPIOB_PIN8) | \ + PIN_PULL_PULLUP(GPIOB_PIN9) | \ + PIN_PULL_PULLUP(GPIOB_PIN10) | \ + PIN_PULL_PULLUP(GPIOB_PIN11) | \ + PIN_PULL_PULLUP(GPIOB_PIN12) | \ + PIN_PULL_PULLUP(GPIOB_PIN13) | \ + PIN_PULL_PULLUP(GPIOB_PIN14) | \ + PIN_PULL_PULLUP(GPIOB_PIN15)) +#define VAL_GPIOB_ODT (PIN_ODT_HIGH(GPIOB_PIN0) | \ + PIN_ODT_HIGH(GPIOB_PIN1) | \ + PIN_ODT_HIGH(GPIOB_PIN2) | \ + PIN_ODT_HIGH(GPIOB_PIN3) | \ + PIN_ODT_HIGH(GPIOB_PIN4) | \ + PIN_ODT_HIGH(GPIOB_PIN5) | \ + PIN_ODT_HIGH(GPIOB_PIN6) | \ + PIN_ODT_HIGH(GPIOB_PIN7) | \ + PIN_ODT_HIGH(GPIOB_PIN8) | \ + PIN_ODT_HIGH(GPIOB_PIN9) | \ + PIN_ODT_HIGH(GPIOB_PIN10) | \ + PIN_ODT_HIGH(GPIOB_PIN11) | \ + PIN_ODT_HIGH(GPIOB_PIN12) | \ + PIN_ODT_HIGH(GPIOB_PIN13) | \ + PIN_ODT_HIGH(GPIOB_PIN14) | \ + PIN_ODT_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_MUXL (PIN_IOMUX_MUX(GPIOB_PIN0, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN1, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN2, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN3, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN4, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN5, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN6, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN7, 0U)) +#define VAL_GPIOB_MUXH (PIN_IOMUX_MUX(GPIOB_PIN8, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN9, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN10, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN11, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN12, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN13, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN14, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN15, 0U)) +#define VAL_GPIOB_HDRV (PIN_HDRV_DISABLED(GPIOB_PIN0) | \ + PIN_HDRV_DISABLED(GPIOB_PIN1) | \ + PIN_HDRV_DISABLED(GPIOB_PIN2) | \ + PIN_HDRV_DISABLED(GPIOB_PIN3) | \ + PIN_HDRV_DISABLED(GPIOB_PIN4) | \ + PIN_HDRV_DISABLED(GPIOB_PIN5) | \ + PIN_HDRV_DISABLED(GPIOB_PIN6) | \ + PIN_HDRV_DISABLED(GPIOB_PIN7) | \ + PIN_HDRV_DISABLED(GPIOB_PIN8) | \ + PIN_HDRV_DISABLED(GPIOB_PIN9) | \ + PIN_HDRV_DISABLED(GPIOB_PIN10) | \ + PIN_HDRV_DISABLED(GPIOB_PIN11) | \ + PIN_HDRV_DISABLED(GPIOB_PIN12) | \ + PIN_HDRV_DISABLED(GPIOB_PIN13) | \ + PIN_HDRV_DISABLED(GPIOB_PIN14) | \ + PIN_HDRV_DISABLED(GPIOB_PIN15)) + +/* + * Port C setup. + * + * PC0 - PIN0 (input pullup). + * PC1 - PIN1 (input pullup). + * PC2 - PIN2 (input pullup). + * PC3 - PIN3 (input pullup). + * PC4 - PIN4 (input pullup). + * PC5 - PIN5 (input pullup). + * PC6 - PIN6 (input pullup). + * PC7 - PIN7 (input pullup). + * PC8 - PIN8 (input pullup). + * PC9 - PIN9 (input pullup). + * PC10 - PIN10 (input pullup). + * PC11 - PIN11 (input pullup). + * PC12 - PIN12 (input pullup). + * PC13 - PIN13 (input pullup). + * PC14 - PIN14 (input pullup). + * PC15 - PIN15 (input pullup). + */ +#define VAL_GPIOC_CFGR (PIN_MODE_INPUT(GPIOC_PIN0) | \ + PIN_MODE_INPUT(GPIOC_PIN1) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_PIN7) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_INPUT(GPIOC_PIN10) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_PIN14) | \ + PIN_MODE_INPUT(GPIOC_PIN15)) +#define VAL_GPIOC_OMODE (PIN_OMODE_PUSHPULL(GPIOC_PIN0) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN1) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN7) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN10) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN14) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN15)) +#define VAL_GPIOC_ODRVR (PIN_ODRVR_STRONGER(GPIOC_PIN0) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN1) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN2) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN3) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN4) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN5) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN6) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN7) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN8) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN9) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN10) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN11) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN12) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN13) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN14) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN15)) +#define VAL_GPIOC_PULL (PIN_PULL_PULLUP(GPIOC_PIN0) | \ + PIN_PULL_PULLUP(GPIOC_PIN1) | \ + PIN_PULL_PULLUP(GPIOC_PIN2) | \ + PIN_PULL_PULLUP(GPIOC_PIN3) | \ + PIN_PULL_PULLUP(GPIOC_PIN4) | \ + PIN_PULL_PULLUP(GPIOC_PIN5) | \ + PIN_PULL_PULLUP(GPIOC_PIN6) | \ + PIN_PULL_PULLUP(GPIOC_PIN7) | \ + PIN_PULL_PULLUP(GPIOC_PIN8) | \ + PIN_PULL_PULLUP(GPIOC_PIN9) | \ + PIN_PULL_PULLUP(GPIOC_PIN10) | \ + PIN_PULL_PULLUP(GPIOC_PIN11) | \ + PIN_PULL_PULLUP(GPIOC_PIN12) | \ + PIN_PULL_PULLUP(GPIOC_PIN13) | \ + PIN_PULL_PULLUP(GPIOC_PIN14) | \ + PIN_PULL_PULLUP(GPIOC_PIN15)) +#define VAL_GPIOC_ODT (PIN_ODT_HIGH(GPIOC_PIN0) | \ + PIN_ODT_HIGH(GPIOC_PIN1) | \ + PIN_ODT_HIGH(GPIOC_PIN2) | \ + PIN_ODT_HIGH(GPIOC_PIN3) | \ + PIN_ODT_HIGH(GPIOC_PIN4) | \ + PIN_ODT_HIGH(GPIOC_PIN5) | \ + PIN_ODT_HIGH(GPIOC_PIN6) | \ + PIN_ODT_HIGH(GPIOC_PIN7) | \ + PIN_ODT_HIGH(GPIOC_PIN8) | \ + PIN_ODT_HIGH(GPIOC_PIN9) | \ + PIN_ODT_HIGH(GPIOC_PIN10) | \ + PIN_ODT_HIGH(GPIOC_PIN11) | \ + PIN_ODT_HIGH(GPIOC_PIN12) | \ + PIN_ODT_HIGH(GPIOC_PIN13) | \ + PIN_ODT_HIGH(GPIOC_PIN14) | \ + PIN_ODT_HIGH(GPIOC_PIN15)) +#define VAL_GPIOC_MUXL (PIN_IOMUX_MUX(GPIOC_PIN0, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN1, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN2, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN3, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN4, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN5, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN6, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN7, 0U)) +#define VAL_GPIOC_MUXH (PIN_IOMUX_MUX(GPIOC_PIN8, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN9, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN10, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN11, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN12, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN13, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN14, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN15, 0U)) +#define VAL_GPIOC_HDRV (PIN_HDRV_DISABLED(GPIOC_PIN0) | \ + PIN_HDRV_DISABLED(GPIOC_PIN1) | \ + PIN_HDRV_DISABLED(GPIOC_PIN2) | \ + PIN_HDRV_DISABLED(GPIOC_PIN3) | \ + PIN_HDRV_DISABLED(GPIOC_PIN4) | \ + PIN_HDRV_DISABLED(GPIOC_PIN5) | \ + PIN_HDRV_DISABLED(GPIOC_PIN6) | \ + PIN_HDRV_DISABLED(GPIOC_PIN7) | \ + PIN_HDRV_DISABLED(GPIOC_PIN8) | \ + PIN_HDRV_DISABLED(GPIOC_PIN9) | \ + PIN_HDRV_DISABLED(GPIOC_PIN10) | \ + PIN_HDRV_DISABLED(GPIOC_PIN11) | \ + PIN_HDRV_DISABLED(GPIOC_PIN12) | \ + PIN_HDRV_DISABLED(GPIOC_PIN13) | \ + PIN_HDRV_DISABLED(GPIOC_PIN14) | \ + PIN_HDRV_DISABLED(GPIOC_PIN15)) + +/* + * Port D setup. + * + * PD2 - PIN2 (input pullup). + */ +#define VAL_GPIOD_CFGR (PIN_MODE_INPUT(GPIOD_PIN2)) +#define VAL_GPIOD_OMODE (PIN_OMODE_PUSHPULL(GPIOD_PIN2)) +#define VAL_GPIOD_ODRVR (PIN_ODRVR_STRONGER(GPIOD_PIN2)) +#define VAL_GPIOD_PULL (PIN_PULL_PULLUP(GPIOD_PIN2)) +#define VAL_GPIOD_ODT (PIN_ODT_HIGH(GPIOD_PIN2)) +#define VAL_GPIOD_MUXL (PIN_IOMUX_MUX(GPIOD_PIN2, 0U)) +#define VAL_GPIOD_MUXH 0U +#define VAL_GPIOD_HDRV (PIN_HDRV_DISABLED(GPIOD_PIN2)) + +/* + * Port F setup. + * + * PF0 - HEXT_IN (input floating). + * PF1 - HEXT_OUT (input floating). + * PF4 - PIN4 (input pullup). + * PF5 - PIN5 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - PIN7 (input pullup). + * PF11 - PIN11 (input pullup). + */ +#define VAL_GPIOF_CFGR (PIN_MODE_INPUT(GPIOF_HEXT_IN) | \ + PIN_MODE_INPUT(GPIOF_HEXT_OUT) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN11)) +#define VAL_GPIOF_OMODE (PIN_OMODE_PUSHPULL(GPIOF_HEXT_IN) | \ + PIN_OMODE_PUSHPULL(GPIOF_HEXT_OUT) | \ + PIN_OMODE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OMODE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OMODE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OMODE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OMODE_PUSHPULL(GPIOF_PIN11)) +#define VAL_GPIOF_ODRVR (PIN_ODRVR_STRONGER(GPIOF_HEXT_IN) | \ + PIN_ODRVR_STRONGER(GPIOF_HEXT_OUT) | \ + PIN_ODRVR_STRONGER(GPIOF_PIN4) | \ + PIN_ODRVR_STRONGER(GPIOF_PIN5) | \ + PIN_ODRVR_STRONGER(GPIOF_PIN6) | \ + PIN_ODRVR_STRONGER(GPIOF_PIN7) | \ + PIN_ODRVR_STRONGER(GPIOF_PIN11)) +#define VAL_GPIOF_PULL (PIN_PULL_FLOATING(GPIOF_HEXT_IN) | \ + PIN_PULL_FLOATING(GPIOF_HEXT_OUT) | \ + PIN_PULL_PULLUP(GPIOF_PIN4) | \ + PIN_PULL_PULLUP(GPIOF_PIN5) | \ + PIN_PULL_PULLUP(GPIOF_PIN6) | \ + PIN_PULL_PULLUP(GPIOF_PIN7) | \ + PIN_PULL_PULLUP(GPIOF_PIN11)) +#define VAL_GPIOF_ODT (PIN_ODT_HIGH(GPIOF_HEXT_IN) | \ + PIN_ODT_HIGH(GPIOF_HEXT_OUT) | \ + PIN_ODT_HIGH(GPIOF_PIN4) | \ + PIN_ODT_HIGH(GPIOF_PIN5) | \ + PIN_ODT_HIGH(GPIOF_PIN6) | \ + PIN_ODT_HIGH(GPIOF_PIN7) | \ + PIN_ODT_HIGH(GPIOF_PIN11)) +#define VAL_GPIOF_MUXL (PIN_IOMUX_MUX(GPIOF_HEXT_IN, 0U) | \ + PIN_IOMUX_MUX(GPIOF_HEXT_OUT, 0U) | \ + PIN_IOMUX_MUX(GPIOF_PIN4, 0U) | \ + PIN_IOMUX_MUX(GPIOF_PIN5, 0U) | \ + PIN_IOMUX_MUX(GPIOF_PIN6, 0U) | \ + PIN_IOMUX_MUX(GPIOF_PIN7, 0U)) +#define VAL_GPIOF_MUXH (PIN_IOMUX_MUX(GPIOF_PIN11, 0U)) +#define VAL_GPIOF_HDRV (PIN_HDRV_DISABLED(GPIOF_HEXT_IN) | \ + PIN_HDRV_DISABLED(GPIOF_HEXT_OUT) | \ + PIN_HDRV_DISABLED(GPIOF_PIN4) | \ + PIN_HDRV_DISABLED(GPIOF_PIN5) | \ + PIN_HDRV_DISABLED(GPIOF_PIN6) | \ + PIN_HDRV_DISABLED(GPIOF_PIN7) | \ + PIN_HDRV_DISABLED(GPIOF_PIN11)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/platforms/chibios/boards/GENERIC_AT32_F402XX/board/board.mk b/platforms/chibios/boards/GENERIC_AT32_F402XX/board/board.mk new file mode 100644 index 00000000000..842e3359059 --- /dev/null +++ b/platforms/chibios/boards/GENERIC_AT32_F402XX/board/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(BOARD_PATH)/board/board.c + +# Required include directories +BOARDINC = $(BOARD_PATH)/board + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/platforms/chibios/boards/GENERIC_AT32_F402XX/configs/config.h b/platforms/chibios/boards/GENERIC_AT32_F402XX/configs/config.h new file mode 100644 index 00000000000..3bef1c143cf --- /dev/null +++ b/platforms/chibios/boards/GENERIC_AT32_F402XX/configs/config.h @@ -0,0 +1,11 @@ +// Copyright 2023-2025 HorrorTroll +// Copyright 2023-2025 Zhaqian +// SPDX-License-Identifier: GPL-2.0-or-later + +#pragma once + +#define BOARD_OTG_VBUSIG + +#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP +# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE +#endif diff --git a/platforms/chibios/boards/GENERIC_AT32_F402XX/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_AT32_F402XX/configs/mcuconf.h new file mode 100644 index 00000000000..0f894b0c18c --- /dev/null +++ b/platforms/chibios/boards/GENERIC_AT32_F402XX/configs/mcuconf.h @@ -0,0 +1,266 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F402 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F402_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 108 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 TRUE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#endif /* MCUCONF_H */ diff --git a/platforms/chibios/boards/GENERIC_AT32_F405XX/board/board.c b/platforms/chibios/boards/GENERIC_AT32_F405XX/board/board.c new file mode 100644 index 00000000000..d413e74f474 --- /dev/null +++ b/platforms/chibios/boards/GENERIC_AT32_F405XX/board/board.c @@ -0,0 +1,159 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" +#include "at32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of AT32 GPIO port setup. + */ +typedef struct { + uint32_t cfgr; + uint32_t omode; + uint32_t odrvr; + uint32_t pull; + uint32_t odt; + uint32_t muxl; + uint32_t muxh; + uint32_t hdrv; +} gpio_setup_t; + +/** + * @brief Type of AT32 GPIO initialization data. + */ +typedef struct { +#if AT32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if AT32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if AT32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if AT32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if AT32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +} gpio_config_t; + +/** + * @brief AT32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if AT32_HAS_GPIOA + {VAL_GPIOA_CFGR, VAL_GPIOA_OMODE, VAL_GPIOA_ODRVR, VAL_GPIOA_PULL, + VAL_GPIOA_ODT, VAL_GPIOA_MUXL, VAL_GPIOA_MUXH, VAL_GPIOA_HDRV}, +#endif +#if AT32_HAS_GPIOB + {VAL_GPIOB_CFGR, VAL_GPIOB_OMODE, VAL_GPIOB_ODRVR, VAL_GPIOB_PULL, + VAL_GPIOB_ODT, VAL_GPIOB_MUXL, VAL_GPIOB_MUXH, VAL_GPIOB_HDRV}, +#endif +#if AT32_HAS_GPIOC + {VAL_GPIOC_CFGR, VAL_GPIOC_OMODE, VAL_GPIOC_ODRVR, VAL_GPIOC_PULL, + VAL_GPIOC_ODT, VAL_GPIOC_MUXL, VAL_GPIOC_MUXH, VAL_GPIOC_HDRV}, +#endif +#if AT32_HAS_GPIOD + {VAL_GPIOD_CFGR, VAL_GPIOD_OMODE, VAL_GPIOD_ODRVR, VAL_GPIOD_PULL, + VAL_GPIOD_ODT, VAL_GPIOD_MUXL, VAL_GPIOD_MUXH, VAL_GPIOD_HDRV}, +#endif +#if AT32_HAS_GPIOF + {VAL_GPIOF_CFGR, VAL_GPIOF_OMODE, VAL_GPIOF_ODRVR, VAL_GPIOF_PULL, + VAL_GPIOF_ODT, VAL_GPIOF_MUXL, VAL_GPIOF_MUXH, VAL_GPIOF_HDRV}, +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(at32_gpio_t *gpiop, const gpio_setup_t *config) { + gpiop->OMODE = config->omode; + gpiop->ODRVR = config->odrvr; + gpiop->PULL = config->pull; + gpiop->ODT = config->odt; + gpiop->MUXL = config->muxl; + gpiop->MUXH = config->muxh; + gpiop->HDRV = config->hdrv; + gpiop->CFGR = config->cfgr; +} + +static void at32_gpio_init(void) { + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + crmResetAHB1(AT32_GPIO_EN_MASK); + crmEnableAHB1(AT32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if AT32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if AT32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if AT32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if AT32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if AT32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + at32_gpio_init(); + at32_clock_init(); +} + +/** + * @brief Board-specific initialization code. + * @note You can add your board-specific code here. + */ +void boardInit(void) { + +} diff --git a/platforms/chibios/boards/GENERIC_AT32_F405XX/board/board.h b/platforms/chibios/boards/GENERIC_AT32_F405XX/board/board.h new file mode 100644 index 00000000000..77821a1b5be --- /dev/null +++ b/platforms/chibios/boards/GENERIC_AT32_F405XX/board/board.h @@ -0,0 +1,633 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * Setup for a Generic AT32F405 board. + */ + +/* + * Board identifier. + */ +#define BOARD_GENERIC_AT32_F405XX +#define BOARD_NAME "GENERIC AT32F405 board" + +/* + * The board has an ULPI USB PHY. + */ +#define BOARD_OTG2_USES_ULPI + +/* + * Board oscillators-related settings. + */ +#if !defined(AT32_LEXTCLK) +#define AT32_LEXTCLK 32768 +#endif + +#if !defined(AT32_HEXTCLK) +#define AT32_HEXTCLK 12000000 +#endif + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define AT32F405KB + +/* + * GPIO settings, allow unused GPIO for smaller chip packages. + */ +#if defined(AT32F405KB) || defined(AT32F405KC) +#define AT32_HAS_GPIOC TRUE +#define AT32_HAS_GPIOD TRUE +#elif defined(AT32F405CB) || defined(AT32F405CC) +#define AT32_HAS_GPIOD TRUE +#endif + +/* + * IO pins assignments. + */ +#define GPIOA_PIN0 0U +#define GPIOA_PIN1 1U +#define GPIOA_PIN2 2U +#define GPIOA_PIN3 3U +#define GPIOA_PIN4 4U +#define GPIOA_PIN5 5U +#define GPIOA_PIN6 6U +#define GPIOA_PIN7 7U +#define GPIOA_PIN8 8U +#define GPIOA_PIN9 9U +#define GPIOA_PIN10 10U +#define GPIOA_PIN11 11U +#define GPIOA_PIN12 12U +#define GPIOA_PIN13 13U +#define GPIOA_PIN14 14U +#define GPIOA_PIN15 15U + +#define GPIOB_PIN0 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_PIN3 3U +#define GPIOB_PIN4 4U +#define GPIOB_PIN5 5U +#define GPIOB_PIN6 6U +#define GPIOB_PIN7 7U +#define GPIOB_PIN8 8U +#define GPIOB_PIN9 9U +#define GPIOB_PIN10 10U +#define GPIOB_PIN12 12U +#define GPIOB_PIN13 13U + +#define GPIOC_PIN0 0U +#define GPIOC_PIN1 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_PIN7 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_PIN14 14U +#define GPIOC_PIN15 15U + +#define GPIOD_PIN2 2U + +#define GPIOF_HEXT_IN 0U +#define GPIOF_HEXT_OUT 1U +#define GPIOF_PIN4 4U +#define GPIOF_PIN5 5U +#define GPIOF_PIN6 6U +#define GPIOF_PIN7 7U +#define GPIOF_PIN11 11U + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the AT32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_MUX(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODT_LOW(n) (0U << (n)) +#define PIN_ODT_HIGH(n) (1U << (n)) +#define PIN_OMODE_PUSHPULL(n) (0U << (n)) +#define PIN_OMODE_OPENDRAIN(n) (1U << (n)) +#define PIN_ODRVR_STRONGER(n) (1U << ((n) * 2U)) +#define PIN_ODRVR_MODERATE(n) (3U << ((n) * 2U)) +#define PIN_PULL_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PULL_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PULL_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_IOMUX_MUX(n, v) ((v) << (((n) % 8U) * 4U)) +#define PIN_WPR_DISABLED(n) (0U << (n)) +#define PIN_WPR_ENABLED(n) (1U << (n)) +#define PIN_HDRV_DISABLED(n) (0U << (n)) +#define PIN_HDRV_ENABLED(n) (1U << (n)) + +/* + * Port A setup. + * + * PA0 - PIN0 (input pullup). + * PA1 - PIN1 (input pullup). + * PA2 - PIN2 (input pullup). + * PA3 - PIN3 (input pullup). + * PA4 - PIN4 (input pullup). + * PA5 - PIN5 (input pullup). + * PA6 - PIN6 (input pullup). + * PA7 - PIN7 (input pullup). + * PA8 - PIN8 (input pullup). + * PA9 - PIN9 (input pullup). + * PA10 - PIN10 (input pullup). + * PA11 - PIN11 (input floating). + * PA12 - PIN12 (input floating). + * PA13 - PIN13 (input pullup). + * PA14 - PIN14 (input pullup). + * PA15 - PIN15 (input pullup). + */ +#define VAL_GPIOA_CFGR (PIN_MODE_INPUT(GPIOA_PIN0) | \ + PIN_MODE_INPUT(GPIOA_PIN1) | \ + PIN_MODE_INPUT(GPIOA_PIN2) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_INPUT(GPIOA_PIN4) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_INPUT(GPIOA_PIN6) | \ + PIN_MODE_INPUT(GPIOA_PIN7) | \ + PIN_MODE_INPUT(GPIOA_PIN8) | \ + PIN_MODE_INPUT(GPIOA_PIN9) | \ + PIN_MODE_INPUT(GPIOA_PIN10) | \ + PIN_MODE_INPUT(GPIOA_PIN11) | \ + PIN_MODE_INPUT(GPIOA_PIN12) | \ + PIN_MODE_INPUT(GPIOA_PIN13) | \ + PIN_MODE_INPUT(GPIOA_PIN14) | \ + PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_OMODE (PIN_OMODE_PUSHPULL(GPIOA_PIN0) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN1) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN2) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN3) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN4) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN5) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN6) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN7) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN8) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN9) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN10) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN11) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN12) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN13) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN14) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_ODRVR (PIN_ODRVR_STRONGER(GPIOA_PIN0) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN1) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN2) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN3) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN4) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN5) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN6) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN7) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN8) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN9) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN10) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN11) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN12) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN13) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN14) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN15)) +#define VAL_GPIOA_PULL (PIN_PULL_PULLUP(GPIOA_PIN0) | \ + PIN_PULL_PULLUP(GPIOA_PIN1) | \ + PIN_PULL_PULLUP(GPIOA_PIN2) | \ + PIN_PULL_PULLUP(GPIOA_PIN3) | \ + PIN_PULL_PULLUP(GPIOA_PIN4) | \ + PIN_PULL_PULLUP(GPIOA_PIN5) | \ + PIN_PULL_PULLUP(GPIOA_PIN6) | \ + PIN_PULL_PULLUP(GPIOA_PIN7) | \ + PIN_PULL_PULLUP(GPIOA_PIN8) | \ + PIN_PULL_PULLUP(GPIOA_PIN9) | \ + PIN_PULL_PULLUP(GPIOA_PIN10) | \ + PIN_PULL_FLOATING(GPIOA_PIN11) | \ + PIN_PULL_FLOATING(GPIOA_PIN12) | \ + PIN_PULL_PULLUP(GPIOA_PIN13) | \ + PIN_PULL_PULLUP(GPIOA_PIN14) | \ + PIN_PULL_PULLUP(GPIOA_PIN15)) +#define VAL_GPIOA_ODT (PIN_ODT_HIGH(GPIOA_PIN0) | \ + PIN_ODT_HIGH(GPIOA_PIN1) | \ + PIN_ODT_HIGH(GPIOA_PIN2) | \ + PIN_ODT_HIGH(GPIOA_PIN3) | \ + PIN_ODT_HIGH(GPIOA_PIN4) | \ + PIN_ODT_HIGH(GPIOA_PIN5) | \ + PIN_ODT_HIGH(GPIOA_PIN6) | \ + PIN_ODT_HIGH(GPIOA_PIN7) | \ + PIN_ODT_HIGH(GPIOA_PIN8) | \ + PIN_ODT_HIGH(GPIOA_PIN9) | \ + PIN_ODT_HIGH(GPIOA_PIN10) | \ + PIN_ODT_HIGH(GPIOA_PIN11) | \ + PIN_ODT_HIGH(GPIOA_PIN12) | \ + PIN_ODT_HIGH(GPIOA_PIN13) | \ + PIN_ODT_HIGH(GPIOA_PIN14) | \ + PIN_ODT_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_MUXL (PIN_IOMUX_MUX(GPIOA_PIN0, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN1, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN2, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN3, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN4, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN5, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN6, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN7, 0U)) +#define VAL_GPIOA_MUXH (PIN_IOMUX_MUX(GPIOA_PIN8, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN9, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN10, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN11, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN12, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN13, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN14, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN15, 0U)) +#define VAL_GPIOA_HDRV (PIN_HDRV_DISABLED(GPIOA_PIN0) | \ + PIN_HDRV_DISABLED(GPIOA_PIN1) | \ + PIN_HDRV_DISABLED(GPIOA_PIN2) | \ + PIN_HDRV_DISABLED(GPIOA_PIN3) | \ + PIN_HDRV_DISABLED(GPIOA_PIN4) | \ + PIN_HDRV_DISABLED(GPIOA_PIN5) | \ + PIN_HDRV_DISABLED(GPIOA_PIN6) | \ + PIN_HDRV_DISABLED(GPIOA_PIN7) | \ + PIN_HDRV_DISABLED(GPIOA_PIN8) | \ + PIN_HDRV_DISABLED(GPIOA_PIN9) | \ + PIN_HDRV_DISABLED(GPIOA_PIN10) | \ + PIN_HDRV_DISABLED(GPIOA_PIN11) | \ + PIN_HDRV_DISABLED(GPIOA_PIN12) | \ + PIN_HDRV_DISABLED(GPIOA_PIN13) | \ + PIN_HDRV_DISABLED(GPIOA_PIN14) | \ + PIN_HDRV_DISABLED(GPIOA_PIN15)) + +/* + * Port B setup. + * + * PB0 - PIN0 (input pullup). + * PB1 - PIN1 (input pullup). + * PB2 - PIN2 (input pullup). + * PB3 - PIN3 (input pullup). + * PB4 - PIN4 (input pullup). + * PB5 - PIN5 (input pullup). + * PB6 - PIN6 (input pullup). + * PB7 - PIN7 (input pullup). + * PB8 - PIN8 (input pullup). + * PB9 - PIN9 (input pullup). + * PB10 - PIN10 (input pullup). + * PB12 - PIN12 (input pullup). + * PB13 - PIN13 (input pullup). + */ +#define VAL_GPIOB_CFGR (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_INPUT(GPIOB_PIN3) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_INPUT(GPIOB_PIN6) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_INPUT(GPIOB_PIN9) | \ + PIN_MODE_INPUT(GPIOB_PIN10) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_INPUT(GPIOB_PIN13)) +#define VAL_GPIOB_OMODE (PIN_OMODE_PUSHPULL(GPIOB_PIN0) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN3) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN4) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN6) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN8) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN9) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN10) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN13)) +#define VAL_GPIOB_ODRVR (PIN_ODRVR_STRONGER(GPIOB_PIN0) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN1) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN2) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN3) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN4) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN5) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN6) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN7) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN8) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN9) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN10) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN12) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN13)) +#define VAL_GPIOB_PULL (PIN_PULL_PULLUP(GPIOB_PIN0) | \ + PIN_PULL_PULLUP(GPIOB_PIN1) | \ + PIN_PULL_PULLUP(GPIOB_PIN2) | \ + PIN_PULL_PULLUP(GPIOB_PIN3) | \ + PIN_PULL_PULLUP(GPIOB_PIN4) | \ + PIN_PULL_PULLUP(GPIOB_PIN5) | \ + PIN_PULL_PULLUP(GPIOB_PIN6) | \ + PIN_PULL_PULLUP(GPIOB_PIN7) | \ + PIN_PULL_PULLUP(GPIOB_PIN8) | \ + PIN_PULL_PULLUP(GPIOB_PIN9) | \ + PIN_PULL_PULLUP(GPIOB_PIN10) | \ + PIN_PULL_PULLUP(GPIOB_PIN12) | \ + PIN_PULL_PULLUP(GPIOB_PIN13)) +#define VAL_GPIOB_ODT (PIN_ODT_HIGH(GPIOB_PIN0) | \ + PIN_ODT_HIGH(GPIOB_PIN1) | \ + PIN_ODT_HIGH(GPIOB_PIN2) | \ + PIN_ODT_HIGH(GPIOB_PIN3) | \ + PIN_ODT_HIGH(GPIOB_PIN4) | \ + PIN_ODT_HIGH(GPIOB_PIN5) | \ + PIN_ODT_HIGH(GPIOB_PIN6) | \ + PIN_ODT_HIGH(GPIOB_PIN7) | \ + PIN_ODT_HIGH(GPIOB_PIN8) | \ + PIN_ODT_HIGH(GPIOB_PIN9) | \ + PIN_ODT_HIGH(GPIOB_PIN10) | \ + PIN_ODT_HIGH(GPIOB_PIN12) | \ + PIN_ODT_HIGH(GPIOB_PIN13)) +#define VAL_GPIOB_MUXL (PIN_IOMUX_MUX(GPIOB_PIN0, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN1, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN2, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN3, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN4, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN5, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN6, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN7, 0U)) +#define VAL_GPIOB_MUXH (PIN_IOMUX_MUX(GPIOB_PIN8, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN9, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN10, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN12, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN13, 0U)) +#define VAL_GPIOB_HDRV (PIN_HDRV_DISABLED(GPIOB_PIN0) | \ + PIN_HDRV_DISABLED(GPIOB_PIN1) | \ + PIN_HDRV_DISABLED(GPIOB_PIN2) | \ + PIN_HDRV_DISABLED(GPIOB_PIN3) | \ + PIN_HDRV_DISABLED(GPIOB_PIN4) | \ + PIN_HDRV_DISABLED(GPIOB_PIN5) | \ + PIN_HDRV_DISABLED(GPIOB_PIN6) | \ + PIN_HDRV_DISABLED(GPIOB_PIN7) | \ + PIN_HDRV_DISABLED(GPIOB_PIN8) | \ + PIN_HDRV_DISABLED(GPIOB_PIN9) | \ + PIN_HDRV_DISABLED(GPIOB_PIN10) | \ + PIN_HDRV_DISABLED(GPIOB_PIN12) | \ + PIN_HDRV_DISABLED(GPIOB_PIN13)) + +/* + * Port C setup. + * + * PC0 - PIN0 (input pullup). + * PC1 - PIN1 (input pullup). + * PC2 - PIN2 (input pullup). + * PC3 - PIN3 (input pullup). + * PC4 - PIN4 (input pullup). + * PC5 - PIN5 (input pullup). + * PC6 - PIN6 (input pullup). + * PC7 - PIN7 (input pullup). + * PC8 - PIN8 (input pullup). + * PC9 - PIN9 (input pullup). + * PC10 - PIN10 (input pullup). + * PC11 - PIN11 (input pullup). + * PC12 - PIN12 (input pullup). + * PC13 - PIN13 (input pullup). + * PC14 - PIN14 (input pullup). + * PC15 - PIN15 (input pullup). + */ +#define VAL_GPIOC_CFGR (PIN_MODE_INPUT(GPIOC_PIN0) | \ + PIN_MODE_INPUT(GPIOC_PIN1) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_PIN7) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_INPUT(GPIOC_PIN10) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_PIN14) | \ + PIN_MODE_INPUT(GPIOC_PIN15)) +#define VAL_GPIOC_OMODE (PIN_OMODE_PUSHPULL(GPIOC_PIN0) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN1) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN7) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN10) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN14) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN15)) +#define VAL_GPIOC_ODRVR (PIN_ODRVR_STRONGER(GPIOC_PIN0) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN1) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN2) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN3) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN4) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN5) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN6) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN7) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN8) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN9) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN10) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN11) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN12) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN13) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN14) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN15)) +#define VAL_GPIOC_PULL (PIN_PULL_PULLUP(GPIOC_PIN0) | \ + PIN_PULL_PULLUP(GPIOC_PIN1) | \ + PIN_PULL_PULLUP(GPIOC_PIN2) | \ + PIN_PULL_PULLUP(GPIOC_PIN3) | \ + PIN_PULL_PULLUP(GPIOC_PIN4) | \ + PIN_PULL_PULLUP(GPIOC_PIN5) | \ + PIN_PULL_PULLUP(GPIOC_PIN6) | \ + PIN_PULL_PULLUP(GPIOC_PIN7) | \ + PIN_PULL_PULLUP(GPIOC_PIN8) | \ + PIN_PULL_PULLUP(GPIOC_PIN9) | \ + PIN_PULL_PULLUP(GPIOC_PIN10) | \ + PIN_PULL_PULLUP(GPIOC_PIN11) | \ + PIN_PULL_PULLUP(GPIOC_PIN12) | \ + PIN_PULL_PULLUP(GPIOC_PIN13) | \ + PIN_PULL_PULLUP(GPIOC_PIN14) | \ + PIN_PULL_PULLUP(GPIOC_PIN15)) +#define VAL_GPIOC_ODT (PIN_ODT_HIGH(GPIOC_PIN0) | \ + PIN_ODT_HIGH(GPIOC_PIN1) | \ + PIN_ODT_HIGH(GPIOC_PIN2) | \ + PIN_ODT_HIGH(GPIOC_PIN3) | \ + PIN_ODT_HIGH(GPIOC_PIN4) | \ + PIN_ODT_HIGH(GPIOC_PIN5) | \ + PIN_ODT_HIGH(GPIOC_PIN6) | \ + PIN_ODT_HIGH(GPIOC_PIN7) | \ + PIN_ODT_HIGH(GPIOC_PIN8) | \ + PIN_ODT_HIGH(GPIOC_PIN9) | \ + PIN_ODT_HIGH(GPIOC_PIN10) | \ + PIN_ODT_HIGH(GPIOC_PIN11) | \ + PIN_ODT_HIGH(GPIOC_PIN12) | \ + PIN_ODT_HIGH(GPIOC_PIN13) | \ + PIN_ODT_HIGH(GPIOC_PIN14) | \ + PIN_ODT_HIGH(GPIOC_PIN15)) +#define VAL_GPIOC_MUXL (PIN_IOMUX_MUX(GPIOC_PIN0, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN1, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN2, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN3, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN4, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN5, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN6, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN7, 0U)) +#define VAL_GPIOC_MUXH (PIN_IOMUX_MUX(GPIOC_PIN8, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN9, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN10, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN11, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN12, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN13, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN14, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN15, 0U)) +#define VAL_GPIOC_HDRV (PIN_HDRV_DISABLED(GPIOC_PIN0) | \ + PIN_HDRV_DISABLED(GPIOC_PIN1) | \ + PIN_HDRV_DISABLED(GPIOC_PIN2) | \ + PIN_HDRV_DISABLED(GPIOC_PIN3) | \ + PIN_HDRV_DISABLED(GPIOC_PIN4) | \ + PIN_HDRV_DISABLED(GPIOC_PIN5) | \ + PIN_HDRV_DISABLED(GPIOC_PIN6) | \ + PIN_HDRV_DISABLED(GPIOC_PIN7) | \ + PIN_HDRV_DISABLED(GPIOC_PIN8) | \ + PIN_HDRV_DISABLED(GPIOC_PIN9) | \ + PIN_HDRV_DISABLED(GPIOC_PIN10) | \ + PIN_HDRV_DISABLED(GPIOC_PIN11) | \ + PIN_HDRV_DISABLED(GPIOC_PIN12) | \ + PIN_HDRV_DISABLED(GPIOC_PIN13) | \ + PIN_HDRV_DISABLED(GPIOC_PIN14) | \ + PIN_HDRV_DISABLED(GPIOC_PIN15)) + +/* + * Port D setup. + * + * PD2 - PIN2 (input pullup). + */ +#define VAL_GPIOD_CFGR (PIN_MODE_INPUT(GPIOD_PIN2)) +#define VAL_GPIOD_OMODE (PIN_OMODE_PUSHPULL(GPIOD_PIN2)) +#define VAL_GPIOD_ODRVR (PIN_ODRVR_STRONGER(GPIOD_PIN2)) +#define VAL_GPIOD_PULL (PIN_PULL_PULLUP(GPIOD_PIN2)) +#define VAL_GPIOD_ODT (PIN_ODT_HIGH(GPIOD_PIN2)) +#define VAL_GPIOD_MUXL (PIN_IOMUX_MUX(GPIOD_PIN2, 0U)) +#define VAL_GPIOD_MUXH 0U +#define VAL_GPIOD_HDRV (PIN_HDRV_DISABLED(GPIOD_PIN2)) + +/* + * Port F setup. + * + * PF0 - HEXT_IN (input floating). + * PF1 - HEXT_OUT (input floating). + * PF4 - PIN4 (input pullup). + * PF5 - PIN5 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - PIN7 (input pullup). + * PF11 - PIN11 (input pullup). + */ +#define VAL_GPIOF_CFGR (PIN_MODE_INPUT(GPIOF_HEXT_IN) | \ + PIN_MODE_INPUT(GPIOF_HEXT_OUT) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN11)) +#define VAL_GPIOF_OMODE (PIN_OMODE_PUSHPULL(GPIOF_HEXT_IN) | \ + PIN_OMODE_PUSHPULL(GPIOF_HEXT_OUT) | \ + PIN_OMODE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OMODE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OMODE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OMODE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OMODE_PUSHPULL(GPIOF_PIN11)) +#define VAL_GPIOF_ODRVR (PIN_ODRVR_STRONGER(GPIOF_HEXT_IN) | \ + PIN_ODRVR_STRONGER(GPIOF_HEXT_OUT) | \ + PIN_ODRVR_STRONGER(GPIOF_PIN4) | \ + PIN_ODRVR_STRONGER(GPIOF_PIN5) | \ + PIN_ODRVR_STRONGER(GPIOF_PIN6) | \ + PIN_ODRVR_STRONGER(GPIOF_PIN7) | \ + PIN_ODRVR_STRONGER(GPIOF_PIN11)) +#define VAL_GPIOF_PULL (PIN_PULL_FLOATING(GPIOF_HEXT_IN) | \ + PIN_PULL_FLOATING(GPIOF_HEXT_OUT) | \ + PIN_PULL_PULLUP(GPIOF_PIN4) | \ + PIN_PULL_PULLUP(GPIOF_PIN5) | \ + PIN_PULL_PULLUP(GPIOF_PIN6) | \ + PIN_PULL_PULLUP(GPIOF_PIN7) | \ + PIN_PULL_PULLUP(GPIOF_PIN11)) +#define VAL_GPIOF_ODT (PIN_ODT_HIGH(GPIOF_HEXT_IN) | \ + PIN_ODT_HIGH(GPIOF_HEXT_OUT) | \ + PIN_ODT_HIGH(GPIOF_PIN4) | \ + PIN_ODT_HIGH(GPIOF_PIN5) | \ + PIN_ODT_HIGH(GPIOF_PIN6) | \ + PIN_ODT_HIGH(GPIOF_PIN7) | \ + PIN_ODT_HIGH(GPIOF_PIN11)) +#define VAL_GPIOF_MUXL (PIN_IOMUX_MUX(GPIOF_HEXT_IN, 0U) | \ + PIN_IOMUX_MUX(GPIOF_HEXT_OUT, 0U) | \ + PIN_IOMUX_MUX(GPIOF_PIN4, 0U) | \ + PIN_IOMUX_MUX(GPIOF_PIN5, 0U) | \ + PIN_IOMUX_MUX(GPIOF_PIN6, 0U) | \ + PIN_IOMUX_MUX(GPIOF_PIN7, 0U)) +#define VAL_GPIOF_MUXH (PIN_IOMUX_MUX(GPIOF_PIN11, 0U)) +#define VAL_GPIOF_HDRV (PIN_HDRV_DISABLED(GPIOF_HEXT_IN) | \ + PIN_HDRV_DISABLED(GPIOF_HEXT_OUT) | \ + PIN_HDRV_DISABLED(GPIOF_PIN4) | \ + PIN_HDRV_DISABLED(GPIOF_PIN5) | \ + PIN_HDRV_DISABLED(GPIOF_PIN6) | \ + PIN_HDRV_DISABLED(GPIOF_PIN7) | \ + PIN_HDRV_DISABLED(GPIOF_PIN11)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/platforms/chibios/boards/GENERIC_AT32_F405XX/board/board.mk b/platforms/chibios/boards/GENERIC_AT32_F405XX/board/board.mk new file mode 100644 index 00000000000..842e3359059 --- /dev/null +++ b/platforms/chibios/boards/GENERIC_AT32_F405XX/board/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(BOARD_PATH)/board/board.c + +# Required include directories +BOARDINC = $(BOARD_PATH)/board + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/platforms/chibios/boards/GENERIC_AT32_F405XX/configs/config.h b/platforms/chibios/boards/GENERIC_AT32_F405XX/configs/config.h new file mode 100644 index 00000000000..407a99ad965 --- /dev/null +++ b/platforms/chibios/boards/GENERIC_AT32_F405XX/configs/config.h @@ -0,0 +1,15 @@ +// Copyright 2023-2025 HorrorTroll +// Copyright 2023-2025 Zhaqian +// SPDX-License-Identifier: GPL-2.0-or-later + +#pragma once + +#if !defined(USB_DRIVER) +# define USB_DRIVER USBD2 +#endif + +#define BOARD_OTG_VBUSIG + +#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP +# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE +#endif diff --git a/platforms/chibios/boards/GENERIC_AT32_F405XX/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_AT32_F405XX/configs/mcuconf.h new file mode 100644 index 00000000000..7b6087b35ab --- /dev/null +++ b/platforms/chibios/boards/GENERIC_AT32_F405XX/configs/mcuconf.h @@ -0,0 +1,271 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F405 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F405_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_USE_OTG2 TRUE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG2_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 +#define AT32_USB_OTG2_RX_FIFO_SIZE 1024 +#define AT32_USE_USB_OTG2_HS_DMA FALSE + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#endif /* MCUCONF_H */ diff --git a/platforms/chibios/boards/GENERIC_AT32_F415XX/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_AT32_F415XX/configs/mcuconf.h index e218e4791aa..52f1cd374c3 100644 --- a/platforms/chibios/boards/GENERIC_AT32_F415XX/configs/mcuconf.h +++ b/platforms/chibios/boards/GENERIC_AT32_F415XX/configs/mcuconf.h @@ -106,6 +106,7 @@ #define AT32_ADC_USE_ADC1 FALSE #define AT32_ADC_ADC1_DMA_PRIORITY 2 #define AT32_ADC_ADC1_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 /* * CAN driver system settings. diff --git a/platforms/chibios/bootloaders/at32_dfu.c b/platforms/chibios/bootloaders/at32_dfu.c index f3a453d0fce..6b057400ff2 100644 --- a/platforms/chibios/bootloaders/at32_dfu.c +++ b/platforms/chibios/bootloaders/at32_dfu.c @@ -1,6 +1,6 @@ // Copyright 2021-2023 QMK -// Copyright 2023-2024 HorrorTroll -// Copyright 2023-2024 Zhaqian +// Copyright 2023-2025 HorrorTroll +// Copyright 2023-2025 Zhaqian // SPDX-License-Identifier: GPL-2.0-or-later #include "bootloader.h" diff --git a/platforms/chibios/chibios_config.h b/platforms/chibios/chibios_config.h index 41546e3e507..a5c01fd3a0c 100644 --- a/platforms/chibios/chibios_config.h +++ b/platforms/chibios/chibios_config.h @@ -154,6 +154,12 @@ # define PAL_MODE_ALTERNATE_OPENDRAIN PAL_MODE_AT32_MUX_OPENDRAIN # define PAL_MODE_ALTERNATE_PUSHPULL PAL_MODE_AT32_MUX_PUSHPULL # define AUDIO_PWM_PAL_MODE PAL_MODE_ALTERNATE_PUSHPULL +# else +# define PAL_OUTPUT_TYPE_OPENDRAIN PAL_AT32_OMODE_OPENDRAIN +# define PAL_OUTPUT_TYPE_PUSHPULL PAL_AT32_OMODE_PUSHPULL +# define PAL_OUTPUT_SPEED_HIGHEST PAL_AT32_ODRVR_STRONGER +# define PAL_PUPDR_FLOATING PAL_AT32_PULL_FLOATING +# define PAL_MODE_ALTERNATE PAL_MODE_MUX # endif #endif diff --git a/platforms/chibios/drivers/analog.c b/platforms/chibios/drivers/analog.c index a916cc9a1d2..6b14af4d9e9 100644 --- a/platforms/chibios/drivers/analog.c +++ b/platforms/chibios/drivers/analog.c @@ -45,7 +45,7 @@ // Otherwise assume V3 #if defined(STM32F0XX) || defined(STM32L0XX) || defined(STM32G0XX) # define USE_ADCV1 -#elif defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415) +#elif defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F402_405) || defined(AT32F415) # define USE_ADCV2 #endif @@ -82,7 +82,7 @@ /* User configurable ADC options */ #ifndef ADC_COUNT -# if defined(RP2040) || defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX) || defined(STM32G0XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415) +# if defined(RP2040) || defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX) || defined(STM32G0XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F402_405) || defined(AT32F415) # define ADC_COUNT 1 # elif defined(STM32F3XX) || defined(STM32G4XX) # define ADC_COUNT 4 @@ -144,10 +144,10 @@ static ADCConversionGroup adcConversionGroup = { .cfgr1 = ADC_CFGR1_CONT | ADC_RESOLUTION, .smpr = ADC_SAMPLING_RATE, #elif defined(USE_ADCV2) -# if !defined(STM32F1XX) && !defined(GD32VF103) && !defined(WB32F3G71xx) && !defined(WB32FQ95xx) && !defined(AT32F415) +# if !defined(STM32F1XX) && !defined(GD32VF103) && !defined(WB32F3G71xx) && !defined(WB32FQ95xx) && !defined(AT32F402_405) && !defined(AT32F415) .cr2 = ADC_CR2_SWSTART, // F103 seem very unhappy with, F401 seems very unhappy without... # endif -# if defined(AT32F415) +# if defined(AT32F402_405) || defined(AT32F415) .spt2 = ADC_SPT2_CSPT_AN0(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN1(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN2(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN3(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN4(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN5(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN6(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN7(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN8(ADC_SAMPLING_RATE) | ADC_SPT2_CSPT_AN9(ADC_SAMPLING_RATE), .spt1 = ADC_SPT1_CSPT_AN10(ADC_SAMPLING_RATE) | ADC_SPT1_CSPT_AN11(ADC_SAMPLING_RATE) | ADC_SPT1_CSPT_AN12(ADC_SAMPLING_RATE) | ADC_SPT1_CSPT_AN13(ADC_SAMPLING_RATE) | ADC_SPT1_CSPT_AN14(ADC_SAMPLING_RATE) | ADC_SPT1_CSPT_AN15(ADC_SAMPLING_RATE), # else @@ -249,7 +249,7 @@ __attribute__((weak)) adc_mux pinToMux(pin_t pin) { case F9: return TO_MUX( ADC_CHANNEL_IN7, 2 ); case F10: return TO_MUX( ADC_CHANNEL_IN8, 2 ); # endif -#elif defined(STM32F1XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415) +#elif defined(STM32F1XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F402_405) || defined(AT32F415) case A0: return TO_MUX( ADC_CHANNEL_IN0, 0 ); case A1: return TO_MUX( ADC_CHANNEL_IN1, 0 ); case A2: return TO_MUX( ADC_CHANNEL_IN2, 0 ); @@ -415,7 +415,7 @@ int16_t adc_read(adc_mux mux) { // TODO: fix previous assumption of only 1 input... adcConversionGroup.chselr = 1 << mux.input; /*no macro to convert N to ADC_CHSELR_CHSEL1*/ #elif defined(USE_ADCV2) -# if defined(AT32F415) +# if defined(AT32F402_405) || defined(AT32F415) adcConversionGroup.osq3 = ADC_OSQ3_OSN1_N(mux.input); # else adcConversionGroup.sqr3 = ADC_SQR3_SQ1_N(mux.input); diff --git a/platforms/chibios/drivers/i2c_master.c b/platforms/chibios/drivers/i2c_master.c index 20850859b5c..f590b57dc0e 100644 --- a/platforms/chibios/drivers/i2c_master.c +++ b/platforms/chibios/drivers/i2c_master.c @@ -100,6 +100,8 @@ static const I2CConfig i2cconfig = { #elif defined(WB32F3G71xx) || defined(WB32FQ95xx) I2C1_OPMODE, I2C1_CLOCK_SPEED, +#elif defined(AT32F402_405) + AT32_CLKCTRL_DIV(I2C1_TIMINGR_PRESC) | AT32_CLKCTRL_SCLD(I2C1_TIMINGR_SCLDEL) | AT32_CLKCTRL_SDAD(I2C1_TIMINGR_SDADEL) | AT32_CLKCTRL_SCLH(I2C1_TIMINGR_SCLH) | AT32_CLKCTRL_SCLL(I2C1_TIMINGR_SCLL), 0, 0 #else // This configures the I2C clock to 400khz assuming a 72Mhz clock // For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html diff --git a/platforms/chibios/drivers/serial_usart.c b/platforms/chibios/drivers/serial_usart.c index becf3afbce1..0ce1659deff 100644 --- a/platforms/chibios/drivers/serial_usart.c +++ b/platforms/chibios/drivers/serial_usart.c @@ -11,7 +11,11 @@ static QMKSerialConfig serial_config = SERIAL_USART_CONFIG; #elif defined(MCU_AT32) /* AT32 MCUs */ static QMKSerialConfig serial_config = { +# if HAL_USE_SERIAL .speed = (SERIAL_USART_SPEED), +# else + .baud = (SERIAL_USART_SPEED), +# endif .ctrl1 = (SERIAL_USART_CTRL1), .ctrl2 = (SERIAL_USART_CTRL2), # if !defined(SERIAL_USART_FULL_DUPLEX) @@ -242,6 +246,8 @@ void serial_transport_driver_master_init(void) { #if defined(MCU_STM32) && defined(SERIAL_USART_PIN_SWAP) serial_config.cr2 |= USART_CR2_SWAP; // master has swapped TX/RX pins +#elif defined(AT32F402_405) && defined(SERIAL_USART_PIN_SWAP) + serial_config.ctrl2 |= USART_CTRL2_TRPSWAP; // master has swapped TX/RX pins #endif usart_driver_start(); diff --git a/platforms/chibios/drivers/spi_master.c b/platforms/chibios/drivers/spi_master.c index 84d027bf49d..26ff5471309 100644 --- a/platforms/chibios/drivers/spi_master.c +++ b/platforms/chibios/drivers/spi_master.c @@ -150,7 +150,7 @@ bool spi_start_extended(spi_start_config_t *start_config) { roundedDivisor <<= 1; } -# if defined(AT32F415) +# if defined(AT32F402_405) || defined(AT32F415) if (roundedDivisor < 2 || roundedDivisor > 1024) { # if (SPI_USE_MUTUAL_EXCLUSION == TRUE) spiReleaseBus(&SPI_DRIVER); @@ -302,7 +302,7 @@ bool spi_start_extended(spi_start_config_t *start_config) { spiConfig.SSPCR0 |= SPI_SSPCR0_SPH; // Clock phase: sample on second edge transition break; } -#elif defined(AT32F415) +#elif defined(AT32F402_405) || defined(AT32F415) spiConfig.ctrl1 = 0; if (start_config->lsb_first) { @@ -326,6 +326,11 @@ bool spi_start_extended(spi_start_config_t *start_config) { switch (roundedDivisor) { case 2: break; +# if defined(AT32F402_405) + case 3: + spiConfig.ctrl2 |= SPI_CTRL2_MDIV3EN; + break; +# endif case 4: spiConfig.ctrl1 |= SPI_CTRL1_MDIV_0; break; diff --git a/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c b/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c index fec4646a5b4..fd1affde7c9 100644 --- a/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c +++ b/platforms/chibios/drivers/wear_leveling/wear_leveling_efl.c @@ -34,7 +34,7 @@ static inline uint32_t detect_flash_size(void) { #elif defined(FLASH_SIZE) return FLASH_SIZE; #elif defined(FLASHSIZE_BASE) -# if defined(QMK_MCU_SERIES_STM32F0XX) || defined(QMK_MCU_SERIES_STM32F1XX) || defined(QMK_MCU_SERIES_STM32F3XX) || defined(QMK_MCU_SERIES_STM32F4XX) || defined(QMK_MCU_SERIES_STM32G4XX) || defined(QMK_MCU_SERIES_STM32L0XX) || defined(QMK_MCU_SERIES_STM32L4XX) || defined(QMK_MCU_SERIES_AT32F415) || defined(QMK_MCU_SERIES_GD32VF103) +# if defined(QMK_MCU_SERIES_STM32F0XX) || defined(QMK_MCU_SERIES_STM32F1XX) || defined(QMK_MCU_SERIES_STM32F3XX) || defined(QMK_MCU_SERIES_STM32F4XX) || defined(QMK_MCU_SERIES_STM32G4XX) || defined(QMK_MCU_SERIES_STM32L0XX) || defined(QMK_MCU_SERIES_STM32L4XX) || defined(QMK_MCU_FAMILY_AT32) || defined(QMK_MCU_SERIES_GD32VF103) return ((*(uint32_t *)FLASHSIZE_BASE) & 0xFFFFU) << 10U; // this register has the flash size in kB, so we convert it to bytes # elif defined(QMK_MCU_SERIES_STM32L1XX) # error This MCU family has an uncommon flash size register definition and has not been implemented. Perhaps try using the true EEPROM on the MCU instead? diff --git a/platforms/chibios/drivers/ws2812_bitbang.c b/platforms/chibios/drivers/ws2812_bitbang.c index a88c5ff619d..7dc42f6dc6b 100644 --- a/platforms/chibios/drivers/ws2812_bitbang.c +++ b/platforms/chibios/drivers/ws2812_bitbang.c @@ -11,7 +11,7 @@ /* Adapted from https://github.com/bigjosh/SimpleNeoPixelDemo/ */ #ifndef WS2812_BITBANG_NOP_FUDGE -# if defined(STM32F0XX) || defined(STM32F1XX) || defined(GD32VF103) || defined(STM32F3XX) || defined(STM32F4XX) || defined(STM32L0XX) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(AT32F415) +# if defined(STM32F0XX) || defined(STM32F1XX) || defined(GD32VF103) || defined(STM32F3XX) || defined(STM32F4XX) || defined(STM32L0XX) || defined(WB32F3G71xx) || defined(WB32FQ95xx) || defined(MCU_AT32) # define WS2812_BITBANG_NOP_FUDGE 0.4 # else # if defined(RP2040) diff --git a/platforms/chibios/drivers/ws2812_pwm.c b/platforms/chibios/drivers/ws2812_pwm.c index 50927b849a4..e5adea9ac88 100644 --- a/platforms/chibios/drivers/ws2812_pwm.c +++ b/platforms/chibios/drivers/ws2812_pwm.c @@ -40,8 +40,14 @@ #if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) && !defined(WS2812_PWM_DMAMUX_ID) # error "please consult your MCU's datasheet and specify in your config.h: #define WS2812_PWM_DMAMUX_ID STM32_DMAMUX1_TIM?_UP" #endif -#if (AT32_DMA_SUPPORTS_DMAMUX == TRUE) && !defined(WS2812_PWM_DMAMUX_CHANNEL) && !defined(WS2812_PWM_DMAMUX_ID) -# error "please consult your MCU's datasheet and specify in your config.h: #define WS2812_PWM_DMAMUX_CHANNEL 1, #define WS2812_PWM_DMAMUX_ID AT32_DMAMUX_TMR?_OVERFLOW" +#if defined(AT32F415) +# if (AT32_DMA_SUPPORTS_DMAMUX == TRUE) && !defined(WS2812_PWM_DMAMUX_CHANNEL) && !defined(WS2812_PWM_DMAMUX_ID) +# error "please consult your MCU's datasheet and specify in your config.h: #define WS2812_PWM_DMAMUX_CHANNEL 1, #define WS2812_PWM_DMAMUX_ID AT32_DMAMUX_TMR?_OVERFLOW" +# endif +#else +# if (AT32_DMA_SUPPORTS_DMAMUX == TRUE) && !defined(WS2812_PWM_DMAMUX_ID) +# error "please consult your MCU's datasheet and specify in your config.h: #define WS2812_PWM_DMAMUX_ID AT32_DMAMUX_TMR?_OVERFLOW" +# endif #endif /* Summarize https://www.st.com/resource/en/application_note/an4013-stm32-crossseries-timer-overview-stmicroelectronics.pdf to @@ -272,7 +278,7 @@ typedef uint32_t ws2812_buffer_t; # define WS2812_PWM_DMA_PERIPHERAL_WIDTH STM32_DMA_CR_PSIZE_HWORD typedef uint16_t ws2812_buffer_t; # endif -#elif defined(AT32F415) +#elif defined(AT32F402_405) || defined(AT32F415) # define WS2812_PWM_DMA_MEMORY_WIDTH AT32_DMA_CCTRL_MWIDTH_BYTE # if defined(WS2812_PWM_TIMER_32BIT) # define WS2812_PWM_DMA_PERIPHERAL_WIDTH AT32_DMA_CCTRL_PWIDTH_WORD @@ -320,7 +326,7 @@ void ws2812_init(void) { [0 ... 3] = {.mode = PWM_OUTPUT_DISABLED, .callback = NULL}, // Channels default to disabled [WS2812_PWM_CHANNEL - 1] = {.mode = WS2812_PWM_OUTPUT_MODE, .callback = NULL}, // Turn on the channel we care about }, -#if defined(AT32F415) +#if defined(AT32F402_405) || defined(AT32F415) .ctrl2 = 0, .iden = AT32_TMR_IDEN_OVFDEN, // DMA on update event for next period #else @@ -337,7 +343,7 @@ void ws2812_init(void) { dmaStreamSetSource(WS2812_PWM_DMA_STREAM, ws2812_frame_buffer); dmaStreamSetDestination(WS2812_PWM_DMA_STREAM, &(WS2812_PWM_DRIVER.tim->CCR[WS2812_PWM_CHANNEL - 1])); // Ziel ist der An-Zeit im Cap-Comp-Register dmaStreamSetMode(WS2812_PWM_DMA_STREAM, WB32_DMA_CHCFG_HWHIF(WS2812_PWM_DMA_CHANNEL) | WB32_DMA_CHCFG_DIR_M2P | WB32_DMA_CHCFG_PSIZE_WORD | WB32_DMA_CHCFG_MSIZE_WORD | WB32_DMA_CHCFG_MINC | WB32_DMA_CHCFG_CIRC | WB32_DMA_CHCFG_TCIE | WB32_DMA_CHCFG_PL(3)); -#elif defined(AT32F415) +#elif defined(AT32F402_405) || defined(AT32F415) dmaStreamAlloc(WS2812_PWM_DMA_STREAM - AT32_DMA_STREAM(0), 10, NULL, NULL); dmaStreamSetPeripheral(WS2812_PWM_DMA_STREAM, &(WS2812_PWM_DRIVER.tmr->CDT[WS2812_PWM_CHANNEL - 1])); // Ziel ist der An-Zeit im Cap-Comp-Register dmaStreamSetMemory0(WS2812_PWM_DMA_STREAM, ws2812_frame_buffer); @@ -356,9 +362,16 @@ void ws2812_init(void) { dmaSetRequestSource(WS2812_PWM_DMA_STREAM, WS2812_PWM_DMAMUX_ID); #endif -#if (AT32_DMA_SUPPORTS_DMAMUX == TRUE) +#if defined(AT32F415) +# if (AT32_DMA_SUPPORTS_DMAMUX == TRUE) // If the MCU has a DMAMUX we need to assign the correct resource dmaSetRequestSource(WS2812_PWM_DMA_STREAM, WS2812_PWM_DMAMUX_CHANNEL, WS2812_PWM_DMAMUX_ID); +# endif +#else +# if (AT32_DMA_SUPPORTS_DMAMUX == TRUE) + // If the MCU has a DMAMUX we need to assign the correct resource + dmaSetRequestSource(WS2812_PWM_DMA_STREAM, WS2812_PWM_DMAMUX_ID); +# endif #endif // Start DMA diff --git a/platforms/chibios/drivers/ws2812_spi.c b/platforms/chibios/drivers/ws2812_spi.c index d1792b871bf..633786462c2 100644 --- a/platforms/chibios/drivers/ws2812_spi.c +++ b/platforms/chibios/drivers/ws2812_spi.c @@ -40,9 +40,13 @@ // Define SPI config speed // baudrate should target 3.2MHz -#if defined(AT32F415) +#if defined(AT32F402_405) || defined(AT32F415) # if WS2812_SPI_DIVISOR == 2 # define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (0) +# if defined(AT32F402_405) +# elif WS2812_SPI_DIVISOR == 3 +# define WS2812_SPI_DIVISOR_CTRL2_MDIV_X (SPI_CTRL2_MDIV3EN) +# endif # elif WS2812_SPI_DIVISOR == 4 # define WS2812_SPI_DIVISOR_CTRL1_MDIV_X (SPI_CTRL1_MDIV_0) # elif WS2812_SPI_DIVISOR == 8 @@ -203,9 +207,9 @@ void ws2812_init(void) { NULL, // error_cb PAL_PORT(WS2812_DI_PIN), PAL_PAD(WS2812_DI_PIN), -# if defined(AT32F415) +# if defined(AT32F402_405) || defined(AT32F415) WS2812_SPI_DIVISOR_CTRL1_MDIV_X, -# if (WS2812_SPI_DIVISOR == 512 || WS2812_SPI_DIVISOR == 1024) +# if (WS2812_SPI_DIVISOR == 3 || WS2812_SPI_DIVISOR == 512 || WS2812_SPI_DIVISOR == 1024) WS2812_SPI_DIVISOR_CTRL2_MDIV_X, # endif 0 diff --git a/platforms/chibios/mcu_selection.mk b/platforms/chibios/mcu_selection.mk index 199bdb23211..9eb462dbf69 100644 --- a/platforms/chibios/mcu_selection.mk +++ b/platforms/chibios/mcu_selection.mk @@ -844,6 +844,74 @@ ifneq ($(findstring WB32FQ95, $(MCU)),) WB32_BOOTLOADER_ADDRESS ?= 0x1FFFE000 endif +ifneq ($(findstring AT32F402, $(MCU)),) + # Cortex version + MCU = cortex-m4 + + # ARM version, CORTEX-M0/M1 are 6, CORTEX-M3/M4/M7 are 7 + ARMV = 7 + + ## chip/board settings + # - the next two should match the directories in + # /os/hal/ports/$(MCU_PORT_NAME)/$(MCU_SERIES) + # OR + # /os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES) + MCU_FAMILY = AT32 + MCU_SERIES = AT32F402_405 + + # Linker script to use + # - it should exist either in /os/common/startup/ARMCMx/compilers/GCC/ld/ + # or /ld/ + MCU_LDSCRIPT ?= AT32F402xB + + # Startup code to use + # - it should exist in /os/common/startup/ARMCMx/compilers/GCC/mk/ + MCU_STARTUP ?= at32f402 + + # Board: it should exist either in /os/hal/boards/, + # /boards/, or drivers/boards/ + BOARD ?= GENERIC_AT32_F402XX + + USE_FPU ?= yes + + # Bootloader address for AT32 DFU + AT32_BOOTLOADER_ADDRESS ?= 0x1FFFA400 +endif + +ifneq ($(findstring AT32F405, $(MCU)),) + # Cortex version + MCU = cortex-m4 + + # ARM version, CORTEX-M0/M1 are 6, CORTEX-M3/M4/M7 are 7 + ARMV = 7 + + ## chip/board settings + # - the next two should match the directories in + # /os/hal/ports/$(MCU_PORT_NAME)/$(MCU_SERIES) + # OR + # /os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES) + MCU_FAMILY = AT32 + MCU_SERIES = AT32F402_405 + + # Linker script to use + # - it should exist either in /os/common/startup/ARMCMx/compilers/GCC/ld/ + # or /ld/ + MCU_LDSCRIPT ?= AT32F405xB + + # Startup code to use + # - it should exist in /os/common/startup/ARMCMx/compilers/GCC/mk/ + MCU_STARTUP ?= at32f405 + + # Board: it should exist either in /os/hal/boards/, + # /boards/, or drivers/boards/ + BOARD ?= GENERIC_AT32_F405XX + + USE_FPU ?= yes + + # Bootloader address for AT32 DFU + AT32_BOOTLOADER_ADDRESS ?= 0x1FFFA400 +endif + ifneq ($(findstring AT32F415, $(MCU)),) # Cortex version MCU = cortex-m4