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annepro2: GPIO cleanup

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This commit is contained in:
bwisn 2021-11-14 08:00:02 +01:00
parent 70273607fd
commit 5f559c2d75
8 changed files with 52 additions and 92 deletions
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8
keyboards/annepro2/annepro2.c
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@ -40,14 +40,6 @@ static const SerialConfig bleUartConfig = {
.speed = 115200,
};
const ioline_t row_list[MATRIX_ROWS] = {
LINE_ROW1, LINE_ROW2, LINE_ROW3, LINE_ROW4, LINE_ROW5,
};
const ioline_t col_list[MATRIX_COLS] = {
LINE_COL1, LINE_COL2, LINE_COL3, LINE_COL4, LINE_COL5, LINE_COL6, LINE_COL7, LINE_COL8, LINE_COL9, LINE_COL10, LINE_COL11, LINE_COL12, LINE_COL13, LINE_COL14,
};
static uint8_t ledMcuWakeup[11] = {0x7b, 0x10, 0x43, 0x10, 0x03, 0x00, 0x00, 0x7d, 0x02, 0x01, 0x02};
ble_capslock_t BLECapsLock = {._dummy = {0}, .caps_lock = false};

6
keyboards/annepro2/boards/ANNEPRO2_C15/board.c
View File

@ -25,12 +25,12 @@
#define PAFIO_H(PORT, LINE, AF) (((PAL_PORT(LINE) == PORT) && (PAL_PAD(LINE) >= 8)) ? (AF << ((PAL_PAD(LINE) - 8) << 2)) : 0)
#define PAFIO(PORT, N, LINE, AF) ((N) ? PAFIO_H(PORT, LINE, AF) : PAFIO_L(PORT, LINE, AF))
#define OUT_BITS(PORT) (PBIT(PORT, LINE_ROW1) | PBIT(PORT, LINE_ROW2) | PBIT(PORT, LINE_ROW3) | PBIT(PORT, LINE_ROW4) | PBIT(PORT, LINE_ROW5) | 0)
#define OUT_BITS(PORT) (PBIT(PORT, C2) | PBIT(PORT, C1) | PBIT(PORT, B5) | PBIT(PORT, B4) | PBIT(PORT, C3) | 0)
#define IN_BITS(PORT) (PBIT(PORT, LINE_COL1) | PBIT(PORT, LINE_COL2) | PBIT(PORT, LINE_COL3) | PBIT(PORT, LINE_COL4) | PBIT(PORT, LINE_COL5) | PBIT(PORT, LINE_COL6) | PBIT(PORT, LINE_COL7) | PBIT(PORT, LINE_COL8) | PBIT(PORT, LINE_COL9) | PBIT(PORT, LINE_COL10) | PBIT(PORT, LINE_COL11) | PBIT(PORT, LINE_COL12) | PBIT(PORT, LINE_COL13) | PBIT(PORT, LINE_COL14) | 0)
#define IN_BITS(PORT) (PBIT(PORT, C4) | PBIT(PORT, C5) | PBIT(PORT, B10) | PBIT(PORT, B11) | PBIT(PORT, C0) | PBIT(PORT, A15) | PBIT(PORT, A8) | PBIT(PORT, A10) | PBIT(PORT, A11) | PBIT(PORT, A12) | PBIT(PORT, A13) | PBIT(PORT, A14) | PBIT(PORT, B2) | PBIT(PORT, B3) | 0)
// Alternate Functions
#define AF_BITS(PORT, N) (PAFIO(PORT, N, LINE_UART_RX, AFIO_USART) | PAFIO(PORT, N, LINE_UART_TX, AFIO_USART) | PAFIO(PORT, N, LINE_BT_UART_TX, AFIO_USART) | PAFIO(PORT, N, LINE_BT_UART_RX, AFIO_USART) | PAFIO(PORT, N, LINE_ROW1, AFIO_GPIO) | PAFIO(PORT, N, LINE_ROW2, AFIO_GPIO) | PAFIO(PORT, N, LINE_ROW3, AFIO_GPIO) | PAFIO(PORT, N, LINE_ROW4, AFIO_GPIO) | PAFIO(PORT, N, LINE_ROW5, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL1, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL2, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL3, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL4, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL5, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL6, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL7, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL8, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL9, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL10, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL11, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL12, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL13, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL14, AFIO_GPIO) | 0)
#define AF_BITS(PORT, N) (PAFIO(PORT, N, LINE_UART_RX, AFIO_USART) | PAFIO(PORT, N, LINE_UART_TX, AFIO_USART) | PAFIO(PORT, N, LINE_BT_UART_TX, AFIO_USART) | PAFIO(PORT, N, LINE_BT_UART_RX, AFIO_USART) | PAFIO(PORT, N, C2, AFIO_GPIO) | PAFIO(PORT, N, C1, AFIO_GPIO) | PAFIO(PORT, N, B5, AFIO_GPIO) | PAFIO(PORT, N, B4, AFIO_GPIO) | PAFIO(PORT, N, C3, AFIO_GPIO) | PAFIO(PORT, N, C4, AFIO_GPIO) | PAFIO(PORT, N, C5, AFIO_GPIO) | PAFIO(PORT, N, B10, AFIO_GPIO) | PAFIO(PORT, N, B11, AFIO_GPIO) | PAFIO(PORT, N, C0, AFIO_GPIO) | PAFIO(PORT, N, A15, AFIO_GPIO) | PAFIO(PORT, N, A8, AFIO_GPIO) | PAFIO(PORT, N, A10, AFIO_GPIO) | PAFIO(PORT, N, A11, AFIO_GPIO) | PAFIO(PORT, N, A12, AFIO_GPIO) | PAFIO(PORT, N, A13, AFIO_GPIO) | PAFIO(PORT, N, A14, AFIO_GPIO) | PAFIO(PORT, N, B2, AFIO_GPIO) | PAFIO(PORT, N, B3, AFIO_GPIO) | 0)
/**
* @brief PAL setup.

42
keyboards/annepro2/boards/ANNEPRO2_C15/board.h
View File

@ -28,46 +28,12 @@
#define FLASH_SIZE (0x10000 - 0x4000) // 64kB - 16kB
/*
* I/O
*/
#define LINE_UART_TX PAL_LINE(IOPORTB, 0) // Master TX, LED RX
#define LINE_UART_RX PAL_LINE(IOPORTB, 1) // Master RX, LED TX
#define LINE_BT_UART_TX PAL_LINE(IOPORTA, 4) // Master TX, BLE RX
#define LINE_BT_UART_RX PAL_LINE(IOPORTA, 5) // Master RX, BLE TX
// outputs (rows are pulled low)
#define LINE_ROW1 PAL_LINE(IOPORTC, 2)
#define LINE_ROW2 PAL_LINE(IOPORTC, 1)
#define LINE_ROW3 PAL_LINE(IOPORTB, 5)
#define LINE_ROW4 PAL_LINE(IOPORTB, 4)
#define LINE_ROW5 PAL_LINE(IOPORTC, 3)
// inputs (columns are sampled)
#define LINE_COL1 PAL_LINE(IOPORTC, 4)
#define LINE_COL2 PAL_LINE(IOPORTC, 5)
#define LINE_COL3 PAL_LINE(IOPORTB, 10)
#define LINE_COL4 PAL_LINE(IOPORTB, 11)
#define LINE_COL5 PAL_LINE(IOPORTC, 0)
#define LINE_COL6 PAL_LINE(IOPORTA, 15)
#define LINE_COL7 PAL_LINE(IOPORTA, 8)
#define LINE_COL8 PAL_LINE(IOPORTA, 10)
#define LINE_COL9 PAL_LINE(IOPORTA, 11)
// PORTA 12,13 conflict with SWD
#define LINE_COL10 PAL_LINE(IOPORTA, 12)
#define LINE_COL11 PAL_LINE(IOPORTA, 13)
#define LINE_COL12 PAL_LINE(IOPORTA, 14)
#define LINE_COL13 PAL_LINE(IOPORTB, 2)
#define LINE_COL14 PAL_LINE(IOPORTB, 3)
#if !defined(_FROM_ASM_)
# ifdef __cplusplus
#ifdef __cplusplus
extern "C" {
# endif
#endif
void boardInit(void);
# ifdef __cplusplus
#ifdef __cplusplus
}
# endif
#endif
#endif /* _FROM_ASM_ */

6
keyboards/annepro2/boards/ANNEPRO2_C18/board.c
View File

@ -25,12 +25,12 @@
#define PAFIO_H(PORT, LINE, AF) (((PAL_PORT(LINE) == PORT) && (PAL_PAD(LINE) >= 8)) ? (AF << ((PAL_PAD(LINE) - 8) << 2)) : 0)
#define PAFIO(PORT, N, LINE, AF) ((N) ? PAFIO_H(PORT, LINE, AF) : PAFIO_L(PORT, LINE, AF))
#define OUT_BITS(PORT) (PBIT(PORT, LINE_ROW1) | PBIT(PORT, LINE_ROW2) | PBIT(PORT, LINE_ROW3) | PBIT(PORT, LINE_ROW4) | PBIT(PORT, LINE_ROW5) | 0)
#define OUT_BITS(PORT) (PBIT(PORT, B5) | PBIT(PORT, B4) | PBIT(PORT, B3) | PBIT(PORT, B2) | PBIT(PORT, D1) | 0)
#define IN_BITS(PORT) (PBIT(PORT, LINE_COL1) | PBIT(PORT, LINE_COL2) | PBIT(PORT, LINE_COL3) | PBIT(PORT, LINE_COL4) | PBIT(PORT, LINE_COL5) | PBIT(PORT, LINE_COL6) | PBIT(PORT, LINE_COL7) | PBIT(PORT, LINE_COL8) | PBIT(PORT, LINE_COL9) | PBIT(PORT, LINE_COL10) | PBIT(PORT, LINE_COL11) | PBIT(PORT, LINE_COL12) | PBIT(PORT, LINE_COL13) | PBIT(PORT, LINE_COL14) | 0)
#define IN_BITS(PORT) (PBIT(PORT, C4) | PBIT(PORT, C5) | PBIT(PORT, D0) | PBIT(PORT, B15) | PBIT(PORT, C11) | PBIT(PORT, A15) | PBIT(PORT, C12) | PBIT(PORT, C13) | PBIT(PORT, A8) | PBIT(PORT, A10) | PBIT(PORT, A11) | PBIT(PORT, A14) | PBIT(PORT, D2) | PBIT(PORT, D3) | 0)
// Alternate Functions
#define AF_BITS(PORT, N) (PAFIO(PORT, N, LINE_UART_RX, AFIO_USART) | PAFIO(PORT, N, LINE_UART_TX, AFIO_USART) | PAFIO(PORT, N, LINE_BT_UART_TX, AFIO_USART) | PAFIO(PORT, N, LINE_BT_UART_RX, AFIO_USART) | PAFIO(PORT, N, LINE_ROW1, AFIO_GPIO) | PAFIO(PORT, N, LINE_ROW2, AFIO_GPIO) | PAFIO(PORT, N, LINE_ROW3, AFIO_GPIO) | PAFIO(PORT, N, LINE_ROW4, AFIO_GPIO) | PAFIO(PORT, N, LINE_ROW5, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL1, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL2, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL3, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL4, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL5, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL6, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL7, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL8, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL9, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL10, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL11, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL12, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL13, AFIO_GPIO) | PAFIO(PORT, N, LINE_COL14, AFIO_GPIO) | 0)
#define AF_BITS(PORT, N) (PAFIO(PORT, N, LINE_UART_RX, AFIO_USART) | PAFIO(PORT, N, LINE_UART_TX, AFIO_USART) | PAFIO(PORT, N, LINE_BT_UART_TX, AFIO_USART) | PAFIO(PORT, N, LINE_BT_UART_RX, AFIO_USART) | PAFIO(PORT, N, B5, AFIO_GPIO) | PAFIO(PORT, N, B4, AFIO_GPIO) | PAFIO(PORT, N, B3, AFIO_GPIO) | PAFIO(PORT, N, B2, AFIO_GPIO) | PAFIO(PORT, N, D1, AFIO_GPIO) | PAFIO(PORT, N, C4, AFIO_GPIO) | PAFIO(PORT, N, C5, AFIO_GPIO) | PAFIO(PORT, N, D0, AFIO_GPIO) | PAFIO(PORT, N, B15, AFIO_GPIO) | PAFIO(PORT, N, C11, AFIO_GPIO) | PAFIO(PORT, N, A15, AFIO_GPIO) | PAFIO(PORT, N, C12, AFIO_GPIO) | PAFIO(PORT, N, C13, AFIO_GPIO) | PAFIO(PORT, N, A8, AFIO_GPIO) | PAFIO(PORT, N, A10, AFIO_GPIO) | PAFIO(PORT, N, A11, AFIO_GPIO) | PAFIO(PORT, N, A14, AFIO_GPIO) | PAFIO(PORT, N, D2, AFIO_GPIO) | PAFIO(PORT, N, D3, AFIO_GPIO) | 0)
/**
* @brief PAL setup.

38
keyboards/annepro2/boards/ANNEPRO2_C18/board.h
View File

@ -22,49 +22,17 @@
/*
* Board identifier.
*/
#define BOARD_NAME "Anne Pro 2"
#define BOARD_NAME "Anne Pro 2"
#define HT32F52342
#define FLASH_SIZE (0x10000 - 0x4000) // 64kB - 16kB
/*
* I/O
*/
#define LINE_UART_TX PAL_LINE(IOPORTB, 0)
#define LINE_UART_RX PAL_LINE(IOPORTB, 1)
#define LINE_BT_UART_TX PAL_LINE(IOPORTA, 4) // Master TX, BLE RX
#define LINE_BT_UART_RX PAL_LINE(IOPORTA, 5) // Master RX, BLE TX
// outputs (rows are pulled low)
#define LINE_ROW1 PAL_LINE(IOPORTB, 5)
#define LINE_ROW2 PAL_LINE(IOPORTB, 4)
#define LINE_ROW3 PAL_LINE(IOPORTB, 3)
#define LINE_ROW4 PAL_LINE(IOPORTB, 2)
#define LINE_ROW5 PAL_LINE(IOPORTD, 1)
// inputs (columns are sampled)
#define LINE_COL1 PAL_LINE(IOPORTC, 4)
#define LINE_COL2 PAL_LINE(IOPORTC, 5)
#define LINE_COL3 PAL_LINE(IOPORTD, 0)
#define LINE_COL4 PAL_LINE(IOPORTB, 15)
#define LINE_COL5 PAL_LINE(IOPORTC, 11)
#define LINE_COL6 PAL_LINE(IOPORTA, 15)
#define LINE_COL7 PAL_LINE(IOPORTC, 12)
#define LINE_COL8 PAL_LINE(IOPORTC, 13)
#define LINE_COL9 PAL_LINE(IOPORTA, 8)
#define LINE_COL10 PAL_LINE(IOPORTA, 10)
#define LINE_COL11 PAL_LINE(IOPORTA, 11)
#define LINE_COL12 PAL_LINE(IOPORTA, 14)
#define LINE_COL13 PAL_LINE(IOPORTD, 2)
#define LINE_COL14 PAL_LINE(IOPORTD, 3)
#define FLASH_SIZE (0x10000 - 0x4000) // 64kB - 16kB
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
void boardInit(void);
#ifdef __cplusplus
}
#endif

18
keyboards/annepro2/c15/config.h
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@ -17,6 +17,8 @@
#pragma once
#include "pin_defs.h"
/* USB Device descriptor parameter */
#define VENDOR_ID 0xfeed
#define PRODUCT_ID 0xac15
@ -27,3 +29,19 @@
#define MATRIX_ROWS 5
#define MATRIX_COLS 14
// layer size: MATRIX_ROWS * MATRIX_COLS * sizeof(uint16_t) = 140 bytes
#define LINE_UART_TX B0 // Master TX, LED RX
#define LINE_UART_RX B1 // Master RX, LED TX
#define LINE_BT_UART_TX A4 // Master TX, BLE RX
#define LINE_BT_UART_RX A5 // Master RX, BLE TX
// outputs (rows are pulled low)
#define MATRIX_ROW_PINS \
{ C2, C1, B5, B4, C3 }
// inputs (columns are sampled)
// PORTA 12,13 conflict with SWD
#define MATRIX_COL_PINS \
{ C4, C5, B10, B11, C0, A15, A8, A10, A11, A12, A13, A14, B2, B3 }

16
keyboards/annepro2/c18/config.h
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@ -17,6 +17,8 @@
#pragma once
#include "pin_defs.h"
/* USB Device descriptor parameter */
#define VENDOR_ID 0xfeed
#define PRODUCT_ID 0xac18
@ -27,3 +29,17 @@
#define MATRIX_ROWS 5
#define MATRIX_COLS 14
// layer size: MATRIX_ROWS * MATRIX_COLS * sizeof(uint16_t) = 140 bytes
#define LINE_UART_TX B0
#define LINE_UART_RX B1
#define LINE_BT_UART_TX A4 // Master TX, BLE RX
#define LINE_BT_UART_RX A5 // Master RX, BLE TX
// outputs (rows are pulled low)
#define MATRIX_ROW_PINS \
{ B5, B4, B3, B2, D1 }
// inputs (columns are sampled)
#define MATRIX_COL_PINS \
{ C4, C5, D0, B15, C11, A15, C12, C13, A8, A10, A11, A14, D2, D3 }

10
keyboards/annepro2/matrix.c
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@ -25,11 +25,11 @@
#include "matrix.h"
#include "annepro2.h"
extern ioline_t row_list[MATRIX_ROWS];
extern ioline_t col_list[MATRIX_COLS];
pin_t row_list[MATRIX_ROWS] = MATRIX_ROW_PINS;
pin_t col_list[MATRIX_COLS] = MATRIX_COL_PINS;
bool matrix_scan_custom(matrix_row_t current_matrix[]) {
bool matrix_has_changed = false;
bool matrix_has_changed = false;
// cache of input ports for columns
static uint16_t port_cache[4];
// scan each row
@ -56,8 +56,8 @@ bool matrix_scan_custom(matrix_row_t current_matrix[]) {
if (current_matrix[row] != data) {
current_matrix[row] = data;
matrix_has_changed = true;
matrix_has_changed = true;
}
}
return matrix_has_changed;
}
}