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fix up chunk
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2fb81fc8cd
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@ -65,7 +65,7 @@
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#endif
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#define IS31FL3729_PWM_REGISTERS_PER_CHUNK 13
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#define IS31FL3729_CHUNK_COUNT (IS31FL3729_PWM_REGISTER_COUNT / IS31FL3729_PWM_REGISTERS_PER_CHUNK)
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#define IS31FL3729_CHUNK_COUNT ((IS31FL3729_PWM_REGISTER_COUNT + IS31FL3729_PWM_REGISTERS_PER_CHUNK - 1) / IS31FL3729_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3729_DRIVER_COUNT] = {
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IS31FL3729_I2C_ADDRESS_1,
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@ -65,7 +65,7 @@
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#endif
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#define IS31FL3729_PWM_REGISTERS_PER_CHUNK 13
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#define IS31FL3729_CHUNK_COUNT (IS31FL3729_PWM_REGISTER_COUNT / IS31FL3729_PWM_REGISTERS_PER_CHUNK)
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#define IS31FL3729_CHUNK_COUNT ((IS31FL3729_PWM_REGISTER_COUNT + IS31FL3729_PWM_REGISTERS_PER_CHUNK - 1) / IS31FL3729_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3729_DRIVER_COUNT] = {
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IS31FL3729_I2C_ADDRESS_1,
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@ -34,7 +34,7 @@
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#endif
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#define IS31FL3731_PWM_REGISTERS_PER_CHUNK 16
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#define IS31FL3731_CHUNK_COUNT (IS31FL3731_PWM_REGISTER_COUNT / IS31FL3731_PWM_REGISTERS_PER_CHUNK)
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#define IS31FL3731_CHUNK_COUNT ((IS31FL3731_PWM_REGISTER_COUNT + IS31FL3731_PWM_REGISTERS_PER_CHUNK - 1) / IS31FL3731_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3731_DRIVER_COUNT] = {
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IS31FL3731_I2C_ADDRESS_1,
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@ -33,7 +33,7 @@
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#endif
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#define IS31FL3731_PWM_REGISTERS_PER_CHUNK 16
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#define IS31FL3731_CHUNK_COUNT (IS31FL3731_PWM_REGISTER_COUNT / IS31FL3731_PWM_REGISTERS_PER_CHUNK)
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#define IS31FL3731_CHUNK_COUNT ((IS31FL3731_PWM_REGISTER_COUNT + IS31FL3731_PWM_REGISTERS_PER_CHUNK - 1) / IS31FL3731_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3731_DRIVER_COUNT] = {
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IS31FL3731_I2C_ADDRESS_1,
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@ -64,7 +64,7 @@
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#endif
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#define IS31FL3733_PWM_REGISTERS_PER_CHUNK 16
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#define IS31FL3733_CHUNK_COUNT (IS31FL3733_PWM_REGISTER_COUNT / IS31FL3733_PWM_REGISTERS_PER_CHUNK)
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#define IS31FL3733_CHUNK_COUNT ((IS31FL3733_PWM_REGISTER_COUNT + IS31FL3733_PWM_REGISTERS_PER_CHUNK - 1) / IS31FL3733_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3733_DRIVER_COUNT] = {
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IS31FL3733_I2C_ADDRESS_1,
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@ -63,7 +63,7 @@
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#endif
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#define IS31FL3733_PWM_REGISTERS_PER_CHUNK 16
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#define IS31FL3733_CHUNK_COUNT (IS31FL3733_PWM_REGISTER_COUNT / IS31FL3733_PWM_REGISTERS_PER_CHUNK)
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#define IS31FL3733_CHUNK_COUNT ((IS31FL3733_PWM_REGISTER_COUNT + IS31FL3733_PWM_REGISTERS_PER_CHUNK - 1) / IS31FL3733_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3733_DRIVER_COUNT] = {
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IS31FL3733_I2C_ADDRESS_1,
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@ -48,7 +48,7 @@
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#endif
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#define IS31FL3736_PWM_REGISTERS_PER_CHUNK 16
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#define IS31FL3736_CHUNK_COUNT (IS31FL3736_PWM_REGISTER_COUNT / IS31FL3736_PWM_REGISTERS_PER_CHUNK)
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#define IS31FL3736_CHUNK_COUNT ((IS31FL3736_PWM_REGISTER_COUNT + IS31FL3736_PWM_REGISTERS_PER_CHUNK - 1) / IS31FL3736_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3736_DRIVER_COUNT] = {
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IS31FL3736_I2C_ADDRESS_1,
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@ -48,7 +48,7 @@
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#endif
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#define IS31FL3736_PWM_REGISTERS_PER_CHUNK 16
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#define IS31FL3736_CHUNK_COUNT (IS31FL3736_PWM_REGISTER_COUNT / IS31FL3736_PWM_REGISTERS_PER_CHUNK)
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#define IS31FL3736_CHUNK_COUNT ((IS31FL3736_PWM_REGISTER_COUNT + IS31FL3736_PWM_REGISTERS_PER_CHUNK - 1) / IS31FL3736_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3736_DRIVER_COUNT] = {
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IS31FL3736_I2C_ADDRESS_1,
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@ -50,7 +50,7 @@
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#endif
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#define IS31FL3737_PWM_REGISTERS_PER_CHUNK 16
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#define IS31FL3737_CHUNK_COUNT (IS31FL3737_PWM_REGISTER_COUNT / IS31FL3737_PWM_REGISTERS_PER_CHUNK)
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#define IS31FL3737_CHUNK_COUNT ((IS31FL3737_PWM_REGISTER_COUNT + IS31FL3737_PWM_REGISTERS_PER_CHUNK - 1) / IS31FL3737_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3737_DRIVER_COUNT] = {
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IS31FL3737_I2C_ADDRESS_1,
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@ -50,7 +50,7 @@
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#endif
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#define IS31FL3737_PWM_REGISTERS_PER_CHUNK 16
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#define IS31FL3737_CHUNK_COUNT (IS31FL3737_PWM_REGISTER_COUNT / IS31FL3737_PWM_REGISTERS_PER_CHUNK)
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#define IS31FL3737_CHUNK_COUNT ((IS31FL3737_PWM_REGISTER_COUNT + IS31FL3737_PWM_REGISTERS_PER_CHUNK - 1) / IS31FL3737_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3737_DRIVER_COUNT] = {
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IS31FL3737_I2C_ADDRESS_1,
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@ -57,8 +57,8 @@
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#define IS31FL3741_PWM_0_REGISTERS_PER_CHUNK 30
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#define IS31FL3741_PWM_1_REGISTERS_PER_CHUNK 19
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#define IS31FL3741_PAGE_0_CHUNK_COUNT (IS31FL3741_PWM_0_REGISTER_COUNT / IS31FL3741_PWM_0_REGISTERS_PER_CHUNK)
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#define IS31FL3741_PAGE_1_CHUNK_COUNT (IS31FL3741_PWM_1_REGISTER_COUNT / IS31FL3741_PWM_1_REGISTERS_PER_CHUNK)
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#define IS31FL3741_PAGE_0_CHUNK_COUNT ((IS31FL3741_PWM_0_REGISTER_COUNT + IS31FL3741_PWM_0_REGISTERS_PER_CHUNK - 1) / IS31FL3741_PWM_0_REGISTERS_PER_CHUNK)
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#define IS31FL3741_PAGE_1_CHUNK_COUNT ((IS31FL3741_PWM_1_REGISTER_COUNT + IS31FL3741_PWM_1_REGISTERS_PER_CHUNK - 1) / IS31FL3741_PWM_1_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3741_DRIVER_COUNT] = {
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IS31FL3741_I2C_ADDRESS_1,
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@ -57,8 +57,8 @@
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#define IS31FL3741_PWM_0_REGISTERS_PER_CHUNK 30
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#define IS31FL3741_PWM_1_REGISTERS_PER_CHUNK 19
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#define IS31FL3741_PAGE_0_CHUNK_COUNT (IS31FL3741_PWM_0_REGISTER_COUNT / IS31FL3741_PWM_0_REGISTERS_PER_CHUNK)
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#define IS31FL3741_PAGE_1_CHUNK_COUNT (IS31FL3741_PWM_1_REGISTER_COUNT / IS31FL3741_PWM_1_REGISTERS_PER_CHUNK)
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#define IS31FL3741_PAGE_0_CHUNK_COUNT ((IS31FL3741_PWM_0_REGISTER_COUNT + IS31FL3741_PWM_0_REGISTERS_PER_CHUNK - 1) / IS31FL3741_PWM_0_REGISTERS_PER_CHUNK)
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#define IS31FL3741_PAGE_1_CHUNK_COUNT ((IS31FL3741_PWM_1_REGISTER_COUNT + IS31FL3741_PWM_1_REGISTERS_PER_CHUNK - 1) / IS31FL3741_PWM_1_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3741_DRIVER_COUNT] = {
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IS31FL3741_I2C_ADDRESS_1,
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@ -55,7 +55,7 @@
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#endif
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#define IS31FL3742A_PWM_REGISTERS_PER_CHUNK 30
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#define IS31FL3742A_CHUNK_COUNT (IS31FL3742A_PWM_REGISTER_COUNT / IS31FL3742A_PWM_REGISTERS_PER_CHUNK)
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#define IS31FL3742A_CHUNK_COUNT ((IS31FL3742A_PWM_REGISTER_COUNT + IS31FL3742A_PWM_REGISTERS_PER_CHUNK - 1) / IS31FL3742A_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3742A_DRIVER_COUNT] = {
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IS31FL3742A_I2C_ADDRESS_1,
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#endif
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#define IS31FL3742A_PWM_REGISTERS_PER_CHUNK 30
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#define IS31FL3742A_CHUNK_COUNT (IS31FL3742A_PWM_REGISTER_COUNT / IS31FL3742A_PWM_REGISTERS_PER_CHUNK)
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#define IS31FL3742A_CHUNK_COUNT ((IS31FL3742A_PWM_REGISTER_COUNT + IS31FL3742A_PWM_REGISTERS_PER_CHUNK - 1) / IS31FL3742A_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3742A_DRIVER_COUNT] = {
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IS31FL3742A_I2C_ADDRESS_1,
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@ -64,7 +64,7 @@
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#endif
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#define IS31FL3743A_PWM_REGISTERS_PER_CHUNK 18
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#define IS31FL3743A_CHUNK_COUNT (IS31FL3743A_PWM_REGISTER_COUNT / IS31FL3743A_PWM_REGISTERS_PER_CHUNK)
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#define IS31FL3743A_CHUNK_COUNT ((IS31FL3743A_PWM_REGISTER_COUNT + IS31FL3743A_PWM_REGISTERS_PER_CHUNK - 1) / IS31FL3743A_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3743A_DRIVER_COUNT] = {
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IS31FL3743A_I2C_ADDRESS_1,
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#endif
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#define IS31FL3743A_PWM_REGISTERS_PER_CHUNK 18
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#define IS31FL3743A_CHUNK_COUNT (IS31FL3743A_PWM_REGISTER_COUNT / IS31FL3743A_PWM_REGISTERS_PER_CHUNK)
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#define IS31FL3743A_CHUNK_COUNT ((IS31FL3743A_PWM_REGISTER_COUNT + IS31FL3743A_PWM_REGISTERS_PER_CHUNK - 1) / IS31FL3743A_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3743A_DRIVER_COUNT] = {
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IS31FL3743A_I2C_ADDRESS_1,
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#endif
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#define IS31FL3745_PWM_REGISTERS_PER_CHUNK 18
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#define IS31FL3745_CHUNK_COUNT (IS31FL3745_PWM_REGISTER_COUNT / IS31FL3745_PWM_REGISTERS_PER_CHUNK)
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#define IS31FL3745_CHUNK_COUNT ((IS31FL3745_PWM_REGISTER_COUNT + IS31FL3745_PWM_REGISTERS_PER_CHUNK - 1) / IS31FL3745_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3745_DRIVER_COUNT] = {
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IS31FL3745_I2C_ADDRESS_1,
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#endif
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#define IS31FL3745_PWM_REGISTERS_PER_CHUNK 18
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#define IS31FL3745_CHUNK_COUNT (IS31FL3745_PWM_REGISTER_COUNT / IS31FL3745_PWM_REGISTERS_PER_CHUNK)
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#define IS31FL3745_CHUNK_COUNT ((IS31FL3745_PWM_REGISTER_COUNT + IS31FL3745_PWM_REGISTERS_PER_CHUNK - 1) / IS31FL3745_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3745_DRIVER_COUNT] = {
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IS31FL3745_I2C_ADDRESS_1,
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#endif
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#define IS31FL3746A_PWM_REGISTERS_PER_CHUNK 18
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#define IS31FL3746A_CHUNK_COUNT (IS31FL3746A_PWM_REGISTER_COUNT / IS31FL3746A_PWM_REGISTERS_PER_CHUNK)
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#define IS31FL3746A_CHUNK_COUNT ((IS31FL3746A_PWM_REGISTER_COUNT + IS31FL3746A_PWM_REGISTERS_PER_CHUNK - 1) / IS31FL3746A_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3746A_DRIVER_COUNT] = {
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IS31FL3746A_I2C_ADDRESS_1,
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#endif
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#define IS31FL3746A_PWM_REGISTERS_PER_CHUNK 18
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#define IS31FL3746A_CHUNK_COUNT (IS31FL3746A_PWM_REGISTER_COUNT / IS31FL3746A_PWM_REGISTERS_PER_CHUNK)
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#define IS31FL3746A_CHUNK_COUNT ((IS31FL3746A_PWM_REGISTER_COUNT + IS31FL3746A_PWM_REGISTERS_PER_CHUNK - 1) / IS31FL3746A_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[IS31FL3746A_DRIVER_COUNT] = {
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IS31FL3746A_I2C_ADDRESS_1,
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@ -39,7 +39,7 @@
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#endif
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#define SNLED27351_PWM_REGISTERS_PER_CHUNK 16
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#define SNLED27351_CHUNK_COUNT (SNLED27351_PWM_REGISTER_COUNT / SNLED27351_PWM_REGISTERS_PER_CHUNK)
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#define SNLED27351_CHUNK_COUNT ((SNLED27351_PWM_REGISTER_COUNT + SNLED27351_PWM_REGISTERS_PER_CHUNK - 1) / SNLED27351_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[SNLED27351_DRIVER_COUNT] = {
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SNLED27351_I2C_ADDRESS_1,
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#endif
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#define SNLED27351_PWM_REGISTERS_PER_CHUNK 16
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#define SNLED27351_CHUNK_COUNT (SNLED27351_PWM_REGISTER_COUNT / SNLED27351_PWM_REGISTERS_PER_CHUNK)
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#define SNLED27351_CHUNK_COUNT ((SNLED27351_PWM_REGISTER_COUNT + SNLED27351_PWM_REGISTERS_PER_CHUNK - 1) / SNLED27351_PWM_REGISTERS_PER_CHUNK)
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const uint8_t i2c_addresses[SNLED27351_DRIVER_COUNT] = {
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SNLED27351_I2C_ADDRESS_1,
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