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Reduce PDI/TPI reset hold period from 1ms to 100us, as the former caused sporadic session issues.

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This commit is contained in:
Dean Camera 2013-11-21 18:41:17 +01:00
parent 52a5016576
commit 52c69331ec
2 changed files with 3 additions and 3 deletions
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2
LUFA/DoxygenPages/ChangeLog.txt
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@ -16,7 +16,7 @@
* - Library Applications: * - Library Applications:
* - Refactored out USB interface IDs in the demo applications into enums (thanks to Laszlo Monda) * - Refactored out USB interface IDs in the demo applications into enums (thanks to Laszlo Monda)
* - AVRISP-MKII Clone Project PDI/TPI frequency increased from 250KHz to 2MHz as it is now stable * - AVRISP-MKII Clone Project PDI/TPI frequency increased from 250KHz to 2MHz as it is now stable
* - Increased TPI/PDI handshake delay to 1ms from 1us to support targets with high amounts of capacitance on their * - Increased TPI/PDI handshake delay to 100us from 1us to support targets with high amounts of capacitance on their
* /RESET lines (thanks to Paul Duke) * /RESET lines (thanks to Paul Duke)
* *
* <b>Fixed:</b> * <b>Fixed:</b>

4
Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c
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@ -52,7 +52,7 @@ void XPROGTarget_EnableTargetPDI(void)
/* Set DATA line high for at least 90ns to disable /RESET functionality */ /* Set DATA line high for at least 90ns to disable /RESET functionality */
PORTD |= (1 << 3); PORTD |= (1 << 3);
_delay_ms(1); _delay_us(100);
/* Set up the synchronous USART for XMEGA communications - 8 data bits, even parity, 2 stop bits */ /* Set up the synchronous USART for XMEGA communications - 8 data bits, even parity, 2 stop bits */
UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1); UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1);
@ -72,7 +72,7 @@ void XPROGTarget_EnableTargetTPI(void)
/* Set /RESET line low for at least 400ns to enable TPI functionality */ /* Set /RESET line low for at least 400ns to enable TPI functionality */
AUX_LINE_DDR |= AUX_LINE_MASK; AUX_LINE_DDR |= AUX_LINE_MASK;
AUX_LINE_PORT &= ~AUX_LINE_MASK; AUX_LINE_PORT &= ~AUX_LINE_MASK;
_delay_ms(1); _delay_us(100);
/* Set Tx and XCK as outputs, Rx as input */ /* Set Tx and XCK as outputs, Rx as input */
DDRD |= (1 << 5) | (1 << 3); DDRD |= (1 << 5) | (1 << 3);