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Slight improvements to the reliability of the software UART in the XPLAINBridge project.

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This commit is contained in:
Dean Camera 2010-06-12 08:39:12 +00:00
parent 931ca42a6e
commit 036a156ff4
3 changed files with 24 additions and 25 deletions
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37
Projects/XPLAINBridge/Lib/SoftUART.c
View File

@ -63,41 +63,38 @@ void SoftUART_Init(void)
EICRA = (1 << ISC01); EICRA = (1 << ISC01);
EIMSK = (1 << INT0); EIMSK = (1 << INT0);
/* Ensure that when the timer is enabled the transmission ISR runs immediately */ /* Start software UART transmission and reception timers */
OCR1B = TCNT1 + 1; TIMSK3 = (1 << OCIE3A);
TCCR3B = (1 << CS30);
/* Start timer 1 with transmission channel force-enabled so that it will immediatly fire */
TCCR1C = (1 << FOC1B);
TIMSK1 = (1 << OCIE1B);
TCCR1B = (1 << CS10); TCCR1B = (1 << CS10);
} }
/** ISR to detect the start of a bit being sent to the software UART. */ /** ISR to detect the start of a bit being sent to the software UART. */
ISR(INT0_vect) ISR(INT0_vect, ISR_BLOCK)
{ {
/* Set reception channel to fire 1.5 bits past the beginning of the start bit */ /* Set reception channel to fire 1.5 bits past the beginning of the start bit */
OCR1A = TCNT1 + ((BIT_TIME * 3) / 2); OCR1A = TCNT1 + (BIT_TIME + (BIT_TIME / 2));
/* Clear the received data temporary variable, reset the current received bit position mask */ /* Clear the received data temporary variable, reset the current received bit position mask */
RX_Data = 0; RX_Data = 0;
RX_BitMask = (1 << 0); RX_BitMask = (1 << 0);
/* Clear reception channel ISR flag in case it is pending */
TIFR1 = (1 << OCF1A);
/* Check that the start bit is still low to prevent noise from triggering a reception */ /* Check that the start bit is still low to prevent noise from triggering a reception */
if (!(SRXPIN & (1 << SRX))) if (!(SRXPIN & (1 << SRX)))
{ {
/* Still low, enable both send and receive channels */ /* Clear reception channel ISR flag in case it is pending */
TIMSK1 = (1 << OCIE1A) | (1 << OCIE1B); TIFR1 = (1 << OCF1A);
/* Clear the start bit detection ISR flag if it is pending */ /* Still low, enable bit receive ISR */
TIMSK1 = (1 << OCIE1A);
/* Clear the start bit detection ISR flag */
EIMSK &= ~(1 << INT0); EIMSK &= ~(1 << INT0);
} }
} }
/** ISR to manage the reception of bits to the software UART. */ /** ISR to manage the reception of bits to the software UART. */
ISR(TIMER1_COMPA_vect) ISR(TIMER1_COMPA_vect, ISR_BLOCK)
{ {
/* Move the reception ISR compare position one bit ahead */ /* Move the reception ISR compare position one bit ahead */
OCR1A += BIT_TIME; OCR1A += BIT_TIME;
@ -118,17 +115,17 @@ ISR(TIMER1_COMPA_vect)
RingBuffer_Insert(&UARTtoUSB_Buffer, RX_Data); RingBuffer_Insert(&UARTtoUSB_Buffer, RX_Data);
/* Disable the reception ISR as all data has now been received, re-enable start bit detection ISR */ /* Disable the reception ISR as all data has now been received, re-enable start bit detection ISR */
TIMSK1 = (1 << OCIE1B); TIMSK1 = 0;
EIMSK |= (1 << INT0); EIFR = (1 << INTF0);
EIFR = (1 << INTF0); EIMSK = (1 << INT0);
} }
} }
/** ISR to manage the transmission of bits via the software UART. */ /** ISR to manage the transmission of bits via the software UART. */
ISR(TIMER1_COMPB_vect) ISR(TIMER3_COMPA_vect, ISR_NOBLOCK)
{ {
/* Move the transmission ISR compare position one bit ahead */ /* Move the transmission ISR compare position one bit ahead */
OCR1B += BIT_TIME; OCR3A += BIT_TIME;
/* Check if transmission has finished */ /* Check if transmission has finished */
if (TX_BitsRemaining) if (TX_BitsRemaining)

2
Projects/XPLAINBridge/XPLAINBridge.c
View File

@ -166,6 +166,8 @@ void SetupHardware(void)
/* Re-enable JTAG debugging */ /* Re-enable JTAG debugging */
MCUCR &= ~(1 << JTD); MCUCR &= ~(1 << JTD);
MCUCR &= ~(1 << JTD); MCUCR &= ~(1 << JTD);
CurrentFirmwareMode = MODE_USART_BRIDGE; // TEMP
} }
/** Event handler for the library USB Configuration Changed event. */ /** Event handler for the library USB Configuration Changed event. */