2020-03-11 04:38:39 +00:00
|
|
|
/* Copyright 2019 Drew Mills
|
|
|
|
|
*
|
|
|
|
|
* This program is free software: you can redistribute it and/or modify
|
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
|
* the Free Software Foundation, either version 2 of the License, or
|
|
|
|
|
* (at your option) any later version.
|
|
|
|
|
*
|
|
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
|
*
|
|
|
|
|
* You should have received a copy of the GNU General Public License
|
|
|
|
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
|
|
|
*/
|
|
|
|
|
|
2020-03-17 00:29:52 +00:00
|
|
|
#include "analog.h"
|
2020-12-11 02:45:24 +00:00
|
|
|
#include <ch.h>
|
2020-03-17 00:29:52 +00:00
|
|
|
#include <hal.h>
|
|
|
|
|
|
|
|
|
|
#if !HAL_USE_ADC
|
|
|
|
|
# error "You need to set HAL_USE_ADC to TRUE in your halconf.h to use the ADC."
|
|
|
|
|
#endif
|
|
|
|
|
|
2023-01-18 23:30:58 +00:00
|
|
|
#if !RP_ADC_USE_ADC1 && !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && !STM32_ADC_USE_ADC3 && !STM32_ADC_USE_ADC4 && !WB32_ADC_USE_ADC1
|
|
|
|
|
# error "You need to set one of the 'xxx_ADC_USE_ADCx' settings to TRUE in your mcuconf.h to use the ADC."
|
2020-03-17 00:29:52 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if STM32_ADC_DUAL_MODE
|
|
|
|
|
# error "STM32 ADC Dual Mode is not supported at this time."
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if STM32_ADCV3_OVERSAMPLING
|
|
|
|
|
# error "STM32 ADCV3 Oversampling is not supported at this time."
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
// Otherwise assume V3
|
|
|
|
|
#if defined(STM32F0XX) || defined(STM32L0XX)
|
|
|
|
|
# define USE_ADCV1
|
2022-11-01 04:04:15 +00:00
|
|
|
#elif defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx)
|
2020-03-17 00:29:52 +00:00
|
|
|
# define USE_ADCV2
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
// BODGE to make v2 look like v1,3 and 4
|
2023-01-18 23:30:58 +00:00
|
|
|
#if defined(USE_ADCV2) || defined(RP2040)
|
2020-03-17 00:29:52 +00:00
|
|
|
# if !defined(ADC_SMPR_SMP_1P5) && defined(ADC_SAMPLE_3)
|
|
|
|
|
# define ADC_SMPR_SMP_1P5 ADC_SAMPLE_3
|
|
|
|
|
# define ADC_SMPR_SMP_7P5 ADC_SAMPLE_15
|
|
|
|
|
# define ADC_SMPR_SMP_13P5 ADC_SAMPLE_28
|
|
|
|
|
# define ADC_SMPR_SMP_28P5 ADC_SAMPLE_56
|
|
|
|
|
# define ADC_SMPR_SMP_41P5 ADC_SAMPLE_84
|
|
|
|
|
# define ADC_SMPR_SMP_55P5 ADC_SAMPLE_112
|
|
|
|
|
# define ADC_SMPR_SMP_71P5 ADC_SAMPLE_144
|
|
|
|
|
# define ADC_SMPR_SMP_239P5 ADC_SAMPLE_480
|
|
|
|
|
# endif
|
|
|
|
|
|
|
|
|
|
# if !defined(ADC_SMPR_SMP_1P5) && defined(ADC_SAMPLE_1P5)
|
|
|
|
|
# define ADC_SMPR_SMP_1P5 ADC_SAMPLE_1P5
|
|
|
|
|
# define ADC_SMPR_SMP_7P5 ADC_SAMPLE_7P5
|
|
|
|
|
# define ADC_SMPR_SMP_13P5 ADC_SAMPLE_13P5
|
|
|
|
|
# define ADC_SMPR_SMP_28P5 ADC_SAMPLE_28P5
|
|
|
|
|
# define ADC_SMPR_SMP_41P5 ADC_SAMPLE_41P5
|
|
|
|
|
# define ADC_SMPR_SMP_55P5 ADC_SAMPLE_55P5
|
|
|
|
|
# define ADC_SMPR_SMP_71P5 ADC_SAMPLE_71P5
|
|
|
|
|
# define ADC_SMPR_SMP_239P5 ADC_SAMPLE_239P5
|
|
|
|
|
# endif
|
|
|
|
|
|
|
|
|
|
// we still sample at 12bit, but scale down to the requested bit range
|
|
|
|
|
# define ADC_CFGR1_RES_12BIT 12
|
|
|
|
|
# define ADC_CFGR1_RES_10BIT 10
|
|
|
|
|
# define ADC_CFGR1_RES_8BIT 8
|
|
|
|
|
# define ADC_CFGR1_RES_6BIT 6
|
|
|
|
|
#endif
|
2020-03-11 04:38:39 +00:00
|
|
|
|
|
|
|
|
/* User configurable ADC options */
|
2020-03-17 00:29:52 +00:00
|
|
|
#ifndef ADC_COUNT
|
2023-01-18 23:30:58 +00:00
|
|
|
# if defined(RP2040) || defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx)
|
2020-03-17 00:29:52 +00:00
|
|
|
# define ADC_COUNT 1
|
|
|
|
|
# elif defined(STM32F3XX)
|
|
|
|
|
# define ADC_COUNT 4
|
|
|
|
|
# else
|
|
|
|
|
# error "ADC_COUNT has not been set for this ARM microcontroller."
|
|
|
|
|
# endif
|
2020-03-11 04:38:39 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef ADC_NUM_CHANNELS
|
2020-03-11 05:11:02 +00:00
|
|
|
# define ADC_NUM_CHANNELS 1
|
2020-03-11 04:38:39 +00:00
|
|
|
#elif ADC_NUM_CHANNELS != 1
|
2020-03-11 05:11:02 +00:00
|
|
|
# error "The ARM ADC implementation currently only supports reading one channel at a time."
|
2020-03-11 04:38:39 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifndef ADC_BUFFER_DEPTH
|
2020-03-17 00:29:52 +00:00
|
|
|
# define ADC_BUFFER_DEPTH 1
|
2020-03-11 04:38:39 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
// For more sampling rate options, look at hal_adc_lld.h in ChibiOS
|
|
|
|
|
#ifndef ADC_SAMPLING_RATE
|
2020-03-11 05:11:02 +00:00
|
|
|
# define ADC_SAMPLING_RATE ADC_SMPR_SMP_1P5
|
2020-03-11 04:38:39 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
// Options are 12, 10, 8, and 6 bit.
|
|
|
|
|
#ifndef ADC_RESOLUTION
|
2022-02-12 18:29:31 +00:00
|
|
|
# ifdef ADC_CFGR_RES_10BITS // ADCv3, ADCv4
|
Update ADC driver for STM32F1xx, STM32F3xx, STM32F4xx (#12403)
* Fix default ADC_RESOLUTION for ADCv3 (and ADCv4)
Recent ChibiOS update removed ADC_CFGR1_RES_10BIT from the ADCv3 headers
(that macro should not have been there, because ADCv3 has CFGR instead of
CFGR1). Fix the default value for ADC_RESOLUTION to use ADC_CFGR_RES_10BITS
if it is defined (that name is used for ADCv3 and ADCv4).
* Update ADC docs to match the actually used resolution
ADC driver for ChibiOS actually uses the 10-bit resolution by default
(probably to match AVR); fix the documentation accordingly. Also add
both ADC_CFGR_RES_10BITS and ADC_CFGR1_RES_10BIT constants (these names
differ according to the ADC implementation in the particular MCU).
* Fix pinToMux() for B12 and B13 on STM32F3xx
Testing on STM32F303CCT6 revealed that the ADC mux values for B12 and
B13 pins were wrong.
* Add support for all possible analog pins on STM32F1xx
Added ADC mux values for pins A0...A7, B0, B1, C0...C5 on STM32F1xx
(they are the same at least for STM32F103x8 and larger F103 devices, and
also F102, F105, F107 families). Actually tested on STM32F103C8T6
(therefore pins C0...C5 were not tested).
Pins F6...F10, which are present on STM32F103x[C-G] in 144-pin packages,
cannot be supported at the moment, because those pins are connected only
to ADC3, but the ChibiOS ADC driver for STM32F1xx supports only ADC1.
* Add support for all possible analog pins on STM32F4xx
Added ADC mux values for pins A0...A7, B0, B1, C0...C5 and optionally
F3...F10 (if STM32_ADC_USE_ADC3 is enabled). These mux values are
apparently the same for all F4xx devices, except some smaller devices may
not have ADC3.
Actually tested on STM32F401CCU6, STM32F401CEU6, STM32F411CEU6 (using
various WeAct “Blackpill” boards); only pins A0...A7, B0, B1 were tested.
Pins F3...F10 are inside `#if STM32_ADC_USE_ADC3` because some devices
which don't have ADC3 also don't have the GPIOF port, therefore the code
which refers to Fx pins does not compile.
* Fix STM32F3xx ADC mux table in documentation
The ADC driver documentation had some errors in the mux table for STM32F3xx.
Fix this table to match the datasheet and the actual code (mux settings for
B12 and B13 were also tested on a real STM32F303CCT6 chip).
* Add STM32F1xx ADC pins to the documentation
* Add STM32F4xx ADC pins to the documentation
2021-04-25 01:15:37 +00:00
|
|
|
# define ADC_RESOLUTION ADC_CFGR_RES_10BITS
|
2022-02-12 18:29:31 +00:00
|
|
|
# else // ADCv1, ADCv5, or the bodge for ADCv2 above
|
Update ADC driver for STM32F1xx, STM32F3xx, STM32F4xx (#12403)
* Fix default ADC_RESOLUTION for ADCv3 (and ADCv4)
Recent ChibiOS update removed ADC_CFGR1_RES_10BIT from the ADCv3 headers
(that macro should not have been there, because ADCv3 has CFGR instead of
CFGR1). Fix the default value for ADC_RESOLUTION to use ADC_CFGR_RES_10BITS
if it is defined (that name is used for ADCv3 and ADCv4).
* Update ADC docs to match the actually used resolution
ADC driver for ChibiOS actually uses the 10-bit resolution by default
(probably to match AVR); fix the documentation accordingly. Also add
both ADC_CFGR_RES_10BITS and ADC_CFGR1_RES_10BIT constants (these names
differ according to the ADC implementation in the particular MCU).
* Fix pinToMux() for B12 and B13 on STM32F3xx
Testing on STM32F303CCT6 revealed that the ADC mux values for B12 and
B13 pins were wrong.
* Add support for all possible analog pins on STM32F1xx
Added ADC mux values for pins A0...A7, B0, B1, C0...C5 on STM32F1xx
(they are the same at least for STM32F103x8 and larger F103 devices, and
also F102, F105, F107 families). Actually tested on STM32F103C8T6
(therefore pins C0...C5 were not tested).
Pins F6...F10, which are present on STM32F103x[C-G] in 144-pin packages,
cannot be supported at the moment, because those pins are connected only
to ADC3, but the ChibiOS ADC driver for STM32F1xx supports only ADC1.
* Add support for all possible analog pins on STM32F4xx
Added ADC mux values for pins A0...A7, B0, B1, C0...C5 and optionally
F3...F10 (if STM32_ADC_USE_ADC3 is enabled). These mux values are
apparently the same for all F4xx devices, except some smaller devices may
not have ADC3.
Actually tested on STM32F401CCU6, STM32F401CEU6, STM32F411CEU6 (using
various WeAct “Blackpill” boards); only pins A0...A7, B0, B1 were tested.
Pins F3...F10 are inside `#if STM32_ADC_USE_ADC3` because some devices
which don't have ADC3 also don't have the GPIOF port, therefore the code
which refers to Fx pins does not compile.
* Fix STM32F3xx ADC mux table in documentation
The ADC driver documentation had some errors in the mux table for STM32F3xx.
Fix this table to match the datasheet and the actual code (mux settings for
B12 and B13 were also tested on a real STM32F303CCT6 chip).
* Add STM32F1xx ADC pins to the documentation
* Add STM32F4xx ADC pins to the documentation
2021-04-25 01:15:37 +00:00
|
|
|
# define ADC_RESOLUTION ADC_CFGR1_RES_10BIT
|
|
|
|
|
# endif
|
2020-03-11 04:38:39 +00:00
|
|
|
#endif
|
|
|
|
|
|
2020-03-11 05:11:02 +00:00
|
|
|
static ADCConfig adcCfg = {};
|
2020-03-11 04:38:39 +00:00
|
|
|
static adcsample_t sampleBuffer[ADC_NUM_CHANNELS * ADC_BUFFER_DEPTH];
|
|
|
|
|
|
|
|
|
|
// Initialize to max number of ADCs, set to empty object to initialize all to false.
|
2020-03-17 00:29:52 +00:00
|
|
|
static bool adcInitialized[ADC_COUNT] = {};
|
|
|
|
|
|
|
|
|
|
// TODO: add back TR handling???
|
|
|
|
|
static ADCConversionGroup adcConversionGroup = {
|
|
|
|
|
.circular = FALSE,
|
|
|
|
|
.num_channels = (uint16_t)(ADC_NUM_CHANNELS),
|
|
|
|
|
#if defined(USE_ADCV1)
|
|
|
|
|
.cfgr1 = ADC_CFGR1_CONT | ADC_RESOLUTION,
|
|
|
|
|
.smpr = ADC_SAMPLING_RATE,
|
|
|
|
|
#elif defined(USE_ADCV2)
|
2022-11-01 04:04:15 +00:00
|
|
|
# if !defined(STM32F1XX) && !defined(GD32VF103) && !defined(WB32F3G71xx) && !defined(WB32FQ95xx)
|
2022-02-12 18:29:31 +00:00
|
|
|
.cr2 = ADC_CR2_SWSTART, // F103 seem very unhappy with, F401 seems very unhappy without...
|
2020-03-17 00:29:52 +00:00
|
|
|
# endif
|
|
|
|
|
.smpr2 = ADC_SMPR2_SMP_AN0(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN1(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN2(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN3(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN4(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN5(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN6(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN7(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN8(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN9(ADC_SAMPLING_RATE),
|
|
|
|
|
.smpr1 = ADC_SMPR1_SMP_AN10(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN11(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN12(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN13(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN14(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN15(ADC_SAMPLING_RATE),
|
2023-01-18 23:30:58 +00:00
|
|
|
#elif defined(RP2040)
|
|
|
|
|
// RP2040 does not have any extra config here
|
2020-03-11 04:38:39 +00:00
|
|
|
#else
|
2020-03-17 00:29:52 +00:00
|
|
|
.cfgr = ADC_CFGR_CONT | ADC_RESOLUTION,
|
|
|
|
|
.smpr = {ADC_SMPR1_SMP_AN0(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN1(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN2(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN3(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN4(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN5(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN6(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN7(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN8(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN9(ADC_SAMPLING_RATE), ADC_SMPR2_SMP_AN10(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN11(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN12(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN13(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN14(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN15(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN16(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN17(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN18(ADC_SAMPLING_RATE)},
|
2020-03-11 04:38:39 +00:00
|
|
|
#endif
|
2020-03-17 00:29:52 +00:00
|
|
|
};
|
2020-03-11 04:38:39 +00:00
|
|
|
|
2020-03-17 00:29:52 +00:00
|
|
|
// clang-format off
|
|
|
|
|
__attribute__((weak)) adc_mux pinToMux(pin_t pin) {
|
|
|
|
|
switch (pin) {
|
2020-03-11 04:38:39 +00:00
|
|
|
#if defined(STM32F0XX)
|
2020-03-17 00:29:52 +00:00
|
|
|
case A0: return TO_MUX( ADC_CHSELR_CHSEL0, 0 );
|
|
|
|
|
case A1: return TO_MUX( ADC_CHSELR_CHSEL1, 0 );
|
|
|
|
|
case A2: return TO_MUX( ADC_CHSELR_CHSEL2, 0 );
|
|
|
|
|
case A3: return TO_MUX( ADC_CHSELR_CHSEL3, 0 );
|
|
|
|
|
case A4: return TO_MUX( ADC_CHSELR_CHSEL4, 0 );
|
|
|
|
|
case A5: return TO_MUX( ADC_CHSELR_CHSEL5, 0 );
|
|
|
|
|
case A6: return TO_MUX( ADC_CHSELR_CHSEL6, 0 );
|
|
|
|
|
case A7: return TO_MUX( ADC_CHSELR_CHSEL7, 0 );
|
|
|
|
|
case B0: return TO_MUX( ADC_CHSELR_CHSEL8, 0 );
|
|
|
|
|
case B1: return TO_MUX( ADC_CHSELR_CHSEL9, 0 );
|
|
|
|
|
case C0: return TO_MUX( ADC_CHSELR_CHSEL10, 0 );
|
|
|
|
|
case C1: return TO_MUX( ADC_CHSELR_CHSEL11, 0 );
|
|
|
|
|
case C2: return TO_MUX( ADC_CHSELR_CHSEL12, 0 );
|
|
|
|
|
case C3: return TO_MUX( ADC_CHSELR_CHSEL13, 0 );
|
|
|
|
|
case C4: return TO_MUX( ADC_CHSELR_CHSEL14, 0 );
|
|
|
|
|
case C5: return TO_MUX( ADC_CHSELR_CHSEL15, 0 );
|
2020-03-11 04:38:39 +00:00
|
|
|
#elif defined(STM32F3XX)
|
2020-03-17 00:29:52 +00:00
|
|
|
case A0: return TO_MUX( ADC_CHANNEL_IN1, 0 );
|
|
|
|
|
case A1: return TO_MUX( ADC_CHANNEL_IN2, 0 );
|
|
|
|
|
case A2: return TO_MUX( ADC_CHANNEL_IN3, 0 );
|
|
|
|
|
case A3: return TO_MUX( ADC_CHANNEL_IN4, 0 );
|
|
|
|
|
case A4: return TO_MUX( ADC_CHANNEL_IN1, 1 );
|
|
|
|
|
case A5: return TO_MUX( ADC_CHANNEL_IN2, 1 );
|
|
|
|
|
case A6: return TO_MUX( ADC_CHANNEL_IN3, 1 );
|
|
|
|
|
case A7: return TO_MUX( ADC_CHANNEL_IN4, 1 );
|
|
|
|
|
case B0: return TO_MUX( ADC_CHANNEL_IN12, 2 );
|
|
|
|
|
case B1: return TO_MUX( ADC_CHANNEL_IN1, 2 );
|
|
|
|
|
case B2: return TO_MUX( ADC_CHANNEL_IN12, 1 );
|
Update ADC driver for STM32F1xx, STM32F3xx, STM32F4xx (#12403)
* Fix default ADC_RESOLUTION for ADCv3 (and ADCv4)
Recent ChibiOS update removed ADC_CFGR1_RES_10BIT from the ADCv3 headers
(that macro should not have been there, because ADCv3 has CFGR instead of
CFGR1). Fix the default value for ADC_RESOLUTION to use ADC_CFGR_RES_10BITS
if it is defined (that name is used for ADCv3 and ADCv4).
* Update ADC docs to match the actually used resolution
ADC driver for ChibiOS actually uses the 10-bit resolution by default
(probably to match AVR); fix the documentation accordingly. Also add
both ADC_CFGR_RES_10BITS and ADC_CFGR1_RES_10BIT constants (these names
differ according to the ADC implementation in the particular MCU).
* Fix pinToMux() for B12 and B13 on STM32F3xx
Testing on STM32F303CCT6 revealed that the ADC mux values for B12 and
B13 pins were wrong.
* Add support for all possible analog pins on STM32F1xx
Added ADC mux values for pins A0...A7, B0, B1, C0...C5 on STM32F1xx
(they are the same at least for STM32F103x8 and larger F103 devices, and
also F102, F105, F107 families). Actually tested on STM32F103C8T6
(therefore pins C0...C5 were not tested).
Pins F6...F10, which are present on STM32F103x[C-G] in 144-pin packages,
cannot be supported at the moment, because those pins are connected only
to ADC3, but the ChibiOS ADC driver for STM32F1xx supports only ADC1.
* Add support for all possible analog pins on STM32F4xx
Added ADC mux values for pins A0...A7, B0, B1, C0...C5 and optionally
F3...F10 (if STM32_ADC_USE_ADC3 is enabled). These mux values are
apparently the same for all F4xx devices, except some smaller devices may
not have ADC3.
Actually tested on STM32F401CCU6, STM32F401CEU6, STM32F411CEU6 (using
various WeAct “Blackpill” boards); only pins A0...A7, B0, B1 were tested.
Pins F3...F10 are inside `#if STM32_ADC_USE_ADC3` because some devices
which don't have ADC3 also don't have the GPIOF port, therefore the code
which refers to Fx pins does not compile.
* Fix STM32F3xx ADC mux table in documentation
The ADC driver documentation had some errors in the mux table for STM32F3xx.
Fix this table to match the datasheet and the actual code (mux settings for
B12 and B13 were also tested on a real STM32F303CCT6 chip).
* Add STM32F1xx ADC pins to the documentation
* Add STM32F4xx ADC pins to the documentation
2021-04-25 01:15:37 +00:00
|
|
|
case B12: return TO_MUX( ADC_CHANNEL_IN3, 3 );
|
|
|
|
|
case B13: return TO_MUX( ADC_CHANNEL_IN5, 2 );
|
2020-03-17 00:29:52 +00:00
|
|
|
case B14: return TO_MUX( ADC_CHANNEL_IN4, 3 );
|
|
|
|
|
case B15: return TO_MUX( ADC_CHANNEL_IN5, 3 );
|
|
|
|
|
case C0: return TO_MUX( ADC_CHANNEL_IN6, 0 ); // Can also be ADC2
|
|
|
|
|
case C1: return TO_MUX( ADC_CHANNEL_IN7, 0 ); // Can also be ADC2
|
|
|
|
|
case C2: return TO_MUX( ADC_CHANNEL_IN8, 0 ); // Can also be ADC2
|
|
|
|
|
case C3: return TO_MUX( ADC_CHANNEL_IN9, 0 ); // Can also be ADC2
|
|
|
|
|
case C4: return TO_MUX( ADC_CHANNEL_IN5, 1 );
|
|
|
|
|
case C5: return TO_MUX( ADC_CHANNEL_IN11, 1 );
|
|
|
|
|
case D8: return TO_MUX( ADC_CHANNEL_IN12, 3 );
|
|
|
|
|
case D9: return TO_MUX( ADC_CHANNEL_IN13, 3 );
|
|
|
|
|
case D10: return TO_MUX( ADC_CHANNEL_IN7, 2 ); // Can also be ADC4
|
|
|
|
|
case D11: return TO_MUX( ADC_CHANNEL_IN8, 2 ); // Can also be ADC4
|
|
|
|
|
case D12: return TO_MUX( ADC_CHANNEL_IN9, 2 ); // Can also be ADC4
|
|
|
|
|
case D13: return TO_MUX( ADC_CHANNEL_IN10, 2 ); // Can also be ADC4
|
|
|
|
|
case D14: return TO_MUX( ADC_CHANNEL_IN11, 2 ); // Can also be ADC4
|
|
|
|
|
case E7: return TO_MUX( ADC_CHANNEL_IN13, 2 );
|
|
|
|
|
case E8: return TO_MUX( ADC_CHANNEL_IN6, 2 ); // Can also be ADC4
|
|
|
|
|
case E9: return TO_MUX( ADC_CHANNEL_IN2, 2 );
|
|
|
|
|
case E10: return TO_MUX( ADC_CHANNEL_IN14, 2 );
|
|
|
|
|
case E11: return TO_MUX( ADC_CHANNEL_IN15, 2 );
|
|
|
|
|
case E12: return TO_MUX( ADC_CHANNEL_IN16, 2 );
|
|
|
|
|
case E13: return TO_MUX( ADC_CHANNEL_IN3, 2 );
|
|
|
|
|
case E14: return TO_MUX( ADC_CHANNEL_IN1, 3 );
|
|
|
|
|
case E15: return TO_MUX( ADC_CHANNEL_IN2, 3 );
|
|
|
|
|
case F2: return TO_MUX( ADC_CHANNEL_IN10, 0 ); // Can also be ADC2
|
|
|
|
|
case F4: return TO_MUX( ADC_CHANNEL_IN5, 0 );
|
Update ADC driver for STM32F1xx, STM32F3xx, STM32F4xx (#12403)
* Fix default ADC_RESOLUTION for ADCv3 (and ADCv4)
Recent ChibiOS update removed ADC_CFGR1_RES_10BIT from the ADCv3 headers
(that macro should not have been there, because ADCv3 has CFGR instead of
CFGR1). Fix the default value for ADC_RESOLUTION to use ADC_CFGR_RES_10BITS
if it is defined (that name is used for ADCv3 and ADCv4).
* Update ADC docs to match the actually used resolution
ADC driver for ChibiOS actually uses the 10-bit resolution by default
(probably to match AVR); fix the documentation accordingly. Also add
both ADC_CFGR_RES_10BITS and ADC_CFGR1_RES_10BIT constants (these names
differ according to the ADC implementation in the particular MCU).
* Fix pinToMux() for B12 and B13 on STM32F3xx
Testing on STM32F303CCT6 revealed that the ADC mux values for B12 and
B13 pins were wrong.
* Add support for all possible analog pins on STM32F1xx
Added ADC mux values for pins A0...A7, B0, B1, C0...C5 on STM32F1xx
(they are the same at least for STM32F103x8 and larger F103 devices, and
also F102, F105, F107 families). Actually tested on STM32F103C8T6
(therefore pins C0...C5 were not tested).
Pins F6...F10, which are present on STM32F103x[C-G] in 144-pin packages,
cannot be supported at the moment, because those pins are connected only
to ADC3, but the ChibiOS ADC driver for STM32F1xx supports only ADC1.
* Add support for all possible analog pins on STM32F4xx
Added ADC mux values for pins A0...A7, B0, B1, C0...C5 and optionally
F3...F10 (if STM32_ADC_USE_ADC3 is enabled). These mux values are
apparently the same for all F4xx devices, except some smaller devices may
not have ADC3.
Actually tested on STM32F401CCU6, STM32F401CEU6, STM32F411CEU6 (using
various WeAct “Blackpill” boards); only pins A0...A7, B0, B1 were tested.
Pins F3...F10 are inside `#if STM32_ADC_USE_ADC3` because some devices
which don't have ADC3 also don't have the GPIOF port, therefore the code
which refers to Fx pins does not compile.
* Fix STM32F3xx ADC mux table in documentation
The ADC driver documentation had some errors in the mux table for STM32F3xx.
Fix this table to match the datasheet and the actual code (mux settings for
B12 and B13 were also tested on a real STM32F303CCT6 chip).
* Add STM32F1xx ADC pins to the documentation
* Add STM32F4xx ADC pins to the documentation
2021-04-25 01:15:37 +00:00
|
|
|
#elif defined(STM32F4XX)
|
2020-03-17 00:29:52 +00:00
|
|
|
case A0: return TO_MUX( ADC_CHANNEL_IN0, 0 );
|
Update ADC driver for STM32F1xx, STM32F3xx, STM32F4xx (#12403)
* Fix default ADC_RESOLUTION for ADCv3 (and ADCv4)
Recent ChibiOS update removed ADC_CFGR1_RES_10BIT from the ADCv3 headers
(that macro should not have been there, because ADCv3 has CFGR instead of
CFGR1). Fix the default value for ADC_RESOLUTION to use ADC_CFGR_RES_10BITS
if it is defined (that name is used for ADCv3 and ADCv4).
* Update ADC docs to match the actually used resolution
ADC driver for ChibiOS actually uses the 10-bit resolution by default
(probably to match AVR); fix the documentation accordingly. Also add
both ADC_CFGR_RES_10BITS and ADC_CFGR1_RES_10BIT constants (these names
differ according to the ADC implementation in the particular MCU).
* Fix pinToMux() for B12 and B13 on STM32F3xx
Testing on STM32F303CCT6 revealed that the ADC mux values for B12 and
B13 pins were wrong.
* Add support for all possible analog pins on STM32F1xx
Added ADC mux values for pins A0...A7, B0, B1, C0...C5 on STM32F1xx
(they are the same at least for STM32F103x8 and larger F103 devices, and
also F102, F105, F107 families). Actually tested on STM32F103C8T6
(therefore pins C0...C5 were not tested).
Pins F6...F10, which are present on STM32F103x[C-G] in 144-pin packages,
cannot be supported at the moment, because those pins are connected only
to ADC3, but the ChibiOS ADC driver for STM32F1xx supports only ADC1.
* Add support for all possible analog pins on STM32F4xx
Added ADC mux values for pins A0...A7, B0, B1, C0...C5 and optionally
F3...F10 (if STM32_ADC_USE_ADC3 is enabled). These mux values are
apparently the same for all F4xx devices, except some smaller devices may
not have ADC3.
Actually tested on STM32F401CCU6, STM32F401CEU6, STM32F411CEU6 (using
various WeAct “Blackpill” boards); only pins A0...A7, B0, B1 were tested.
Pins F3...F10 are inside `#if STM32_ADC_USE_ADC3` because some devices
which don't have ADC3 also don't have the GPIOF port, therefore the code
which refers to Fx pins does not compile.
* Fix STM32F3xx ADC mux table in documentation
The ADC driver documentation had some errors in the mux table for STM32F3xx.
Fix this table to match the datasheet and the actual code (mux settings for
B12 and B13 were also tested on a real STM32F303CCT6 chip).
* Add STM32F1xx ADC pins to the documentation
* Add STM32F4xx ADC pins to the documentation
2021-04-25 01:15:37 +00:00
|
|
|
case A1: return TO_MUX( ADC_CHANNEL_IN1, 0 );
|
|
|
|
|
case A2: return TO_MUX( ADC_CHANNEL_IN2, 0 );
|
|
|
|
|
case A3: return TO_MUX( ADC_CHANNEL_IN3, 0 );
|
|
|
|
|
case A4: return TO_MUX( ADC_CHANNEL_IN4, 0 );
|
|
|
|
|
case A5: return TO_MUX( ADC_CHANNEL_IN5, 0 );
|
|
|
|
|
case A6: return TO_MUX( ADC_CHANNEL_IN6, 0 );
|
|
|
|
|
case A7: return TO_MUX( ADC_CHANNEL_IN7, 0 );
|
|
|
|
|
case B0: return TO_MUX( ADC_CHANNEL_IN8, 0 );
|
|
|
|
|
case B1: return TO_MUX( ADC_CHANNEL_IN9, 0 );
|
|
|
|
|
case C0: return TO_MUX( ADC_CHANNEL_IN10, 0 );
|
|
|
|
|
case C1: return TO_MUX( ADC_CHANNEL_IN11, 0 );
|
|
|
|
|
case C2: return TO_MUX( ADC_CHANNEL_IN12, 0 );
|
|
|
|
|
case C3: return TO_MUX( ADC_CHANNEL_IN13, 0 );
|
|
|
|
|
case C4: return TO_MUX( ADC_CHANNEL_IN14, 0 );
|
|
|
|
|
case C5: return TO_MUX( ADC_CHANNEL_IN15, 0 );
|
|
|
|
|
# if STM32_ADC_USE_ADC3
|
|
|
|
|
case F3: return TO_MUX( ADC_CHANNEL_IN9, 2 );
|
|
|
|
|
case F4: return TO_MUX( ADC_CHANNEL_IN14, 2 );
|
|
|
|
|
case F5: return TO_MUX( ADC_CHANNEL_IN15, 2 );
|
|
|
|
|
case F6: return TO_MUX( ADC_CHANNEL_IN4, 2 );
|
|
|
|
|
case F7: return TO_MUX( ADC_CHANNEL_IN5, 2 );
|
|
|
|
|
case F8: return TO_MUX( ADC_CHANNEL_IN6, 2 );
|
|
|
|
|
case F9: return TO_MUX( ADC_CHANNEL_IN7, 2 );
|
|
|
|
|
case F10: return TO_MUX( ADC_CHANNEL_IN8, 2 );
|
|
|
|
|
# endif
|
2022-11-01 04:04:15 +00:00
|
|
|
#elif defined(STM32F1XX) || defined(GD32VF103) || defined(WB32F3G71xx) || defined(WB32FQ95xx)
|
2020-03-17 00:29:52 +00:00
|
|
|
case A0: return TO_MUX( ADC_CHANNEL_IN0, 0 );
|
Update ADC driver for STM32F1xx, STM32F3xx, STM32F4xx (#12403)
* Fix default ADC_RESOLUTION for ADCv3 (and ADCv4)
Recent ChibiOS update removed ADC_CFGR1_RES_10BIT from the ADCv3 headers
(that macro should not have been there, because ADCv3 has CFGR instead of
CFGR1). Fix the default value for ADC_RESOLUTION to use ADC_CFGR_RES_10BITS
if it is defined (that name is used for ADCv3 and ADCv4).
* Update ADC docs to match the actually used resolution
ADC driver for ChibiOS actually uses the 10-bit resolution by default
(probably to match AVR); fix the documentation accordingly. Also add
both ADC_CFGR_RES_10BITS and ADC_CFGR1_RES_10BIT constants (these names
differ according to the ADC implementation in the particular MCU).
* Fix pinToMux() for B12 and B13 on STM32F3xx
Testing on STM32F303CCT6 revealed that the ADC mux values for B12 and
B13 pins were wrong.
* Add support for all possible analog pins on STM32F1xx
Added ADC mux values for pins A0...A7, B0, B1, C0...C5 on STM32F1xx
(they are the same at least for STM32F103x8 and larger F103 devices, and
also F102, F105, F107 families). Actually tested on STM32F103C8T6
(therefore pins C0...C5 were not tested).
Pins F6...F10, which are present on STM32F103x[C-G] in 144-pin packages,
cannot be supported at the moment, because those pins are connected only
to ADC3, but the ChibiOS ADC driver for STM32F1xx supports only ADC1.
* Add support for all possible analog pins on STM32F4xx
Added ADC mux values for pins A0...A7, B0, B1, C0...C5 and optionally
F3...F10 (if STM32_ADC_USE_ADC3 is enabled). These mux values are
apparently the same for all F4xx devices, except some smaller devices may
not have ADC3.
Actually tested on STM32F401CCU6, STM32F401CEU6, STM32F411CEU6 (using
various WeAct “Blackpill” boards); only pins A0...A7, B0, B1 were tested.
Pins F3...F10 are inside `#if STM32_ADC_USE_ADC3` because some devices
which don't have ADC3 also don't have the GPIOF port, therefore the code
which refers to Fx pins does not compile.
* Fix STM32F3xx ADC mux table in documentation
The ADC driver documentation had some errors in the mux table for STM32F3xx.
Fix this table to match the datasheet and the actual code (mux settings for
B12 and B13 were also tested on a real STM32F303CCT6 chip).
* Add STM32F1xx ADC pins to the documentation
* Add STM32F4xx ADC pins to the documentation
2021-04-25 01:15:37 +00:00
|
|
|
case A1: return TO_MUX( ADC_CHANNEL_IN1, 0 );
|
|
|
|
|
case A2: return TO_MUX( ADC_CHANNEL_IN2, 0 );
|
|
|
|
|
case A3: return TO_MUX( ADC_CHANNEL_IN3, 0 );
|
|
|
|
|
case A4: return TO_MUX( ADC_CHANNEL_IN4, 0 );
|
|
|
|
|
case A5: return TO_MUX( ADC_CHANNEL_IN5, 0 );
|
|
|
|
|
case A6: return TO_MUX( ADC_CHANNEL_IN6, 0 );
|
|
|
|
|
case A7: return TO_MUX( ADC_CHANNEL_IN7, 0 );
|
|
|
|
|
case B0: return TO_MUX( ADC_CHANNEL_IN8, 0 );
|
|
|
|
|
case B1: return TO_MUX( ADC_CHANNEL_IN9, 0 );
|
|
|
|
|
case C0: return TO_MUX( ADC_CHANNEL_IN10, 0 );
|
|
|
|
|
case C1: return TO_MUX( ADC_CHANNEL_IN11, 0 );
|
|
|
|
|
case C2: return TO_MUX( ADC_CHANNEL_IN12, 0 );
|
|
|
|
|
case C3: return TO_MUX( ADC_CHANNEL_IN13, 0 );
|
|
|
|
|
case C4: return TO_MUX( ADC_CHANNEL_IN14, 0 );
|
|
|
|
|
case C5: return TO_MUX( ADC_CHANNEL_IN15, 0 );
|
|
|
|
|
// STM32F103x[C-G] in 144-pin packages also have analog inputs on F6...F10, but they are on ADC3, and the
|
|
|
|
|
// ChibiOS ADC driver for STM32F1xx currently supports only ADC1, therefore these pins are not usable.
|
2023-01-18 23:30:58 +00:00
|
|
|
#elif defined(RP2040)
|
|
|
|
|
case 26U: return TO_MUX(0, 0);
|
|
|
|
|
case 27U: return TO_MUX(1, 0);
|
|
|
|
|
case 28U: return TO_MUX(2, 0);
|
|
|
|
|
case 29U: return TO_MUX(3, 0);
|
2020-03-11 04:38:39 +00:00
|
|
|
#endif
|
2020-03-17 00:29:52 +00:00
|
|
|
}
|
2020-03-11 04:38:39 +00:00
|
|
|
|
2020-03-17 00:29:52 +00:00
|
|
|
// return an adc that would never be used so intToADCDriver will bail out
|
|
|
|
|
return TO_MUX(0, 0xFF);
|
|
|
|
|
}
|
|
|
|
|
// clang-format on
|
2020-03-11 04:38:39 +00:00
|
|
|
|
2020-03-17 00:29:52 +00:00
|
|
|
static inline ADCDriver* intToADCDriver(uint8_t adcInt) {
|
2020-03-11 04:38:39 +00:00
|
|
|
switch (adcInt) {
|
2023-01-18 23:30:58 +00:00
|
|
|
#if RP_ADC_USE_ADC1 || STM32_ADC_USE_ADC1 || WB32_ADC_USE_ADC1
|
2020-03-17 00:29:52 +00:00
|
|
|
case 0:
|
|
|
|
|
return &ADCD1;
|
2020-03-11 04:38:39 +00:00
|
|
|
#endif
|
|
|
|
|
#if STM32_ADC_USE_ADC2
|
2020-03-17 00:29:52 +00:00
|
|
|
case 1:
|
|
|
|
|
return &ADCD2;
|
2020-03-11 04:38:39 +00:00
|
|
|
#endif
|
|
|
|
|
#if STM32_ADC_USE_ADC3
|
2020-03-17 00:29:52 +00:00
|
|
|
case 2:
|
|
|
|
|
return &ADCD3;
|
2020-03-11 04:38:39 +00:00
|
|
|
#endif
|
|
|
|
|
#if STM32_ADC_USE_ADC4
|
2020-03-17 00:29:52 +00:00
|
|
|
case 3:
|
|
|
|
|
return &ADCD4;
|
2020-03-11 04:38:39 +00:00
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
2020-03-17 00:29:52 +00:00
|
|
|
return NULL;
|
2020-03-11 04:38:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void manageAdcInitializationDriver(uint8_t adc, ADCDriver* adcDriver) {
|
|
|
|
|
if (!adcInitialized[adc]) {
|
|
|
|
|
adcStart(adcDriver, &adcCfg);
|
|
|
|
|
adcInitialized[adc] = true;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2020-03-17 00:29:52 +00:00
|
|
|
int16_t analogReadPin(pin_t pin) {
|
|
|
|
|
palSetLineMode(pin, PAL_MODE_INPUT_ANALOG);
|
2020-03-11 04:38:39 +00:00
|
|
|
|
2020-03-17 00:29:52 +00:00
|
|
|
return adc_read(pinToMux(pin));
|
2020-03-11 04:38:39 +00:00
|
|
|
}
|
|
|
|
|
|
2020-03-17 00:29:52 +00:00
|
|
|
int16_t analogReadPinAdc(pin_t pin, uint8_t adc) {
|
|
|
|
|
palSetLineMode(pin, PAL_MODE_INPUT_ANALOG);
|
2020-03-11 04:38:39 +00:00
|
|
|
|
2020-03-17 00:29:52 +00:00
|
|
|
adc_mux target = pinToMux(pin);
|
|
|
|
|
target.adc = adc;
|
2020-03-11 04:38:39 +00:00
|
|
|
return adc_read(target);
|
|
|
|
|
}
|
|
|
|
|
|
2020-03-17 00:29:52 +00:00
|
|
|
int16_t adc_read(adc_mux mux) {
|
|
|
|
|
#if defined(USE_ADCV1)
|
|
|
|
|
// TODO: fix previous assumption of only 1 input...
|
|
|
|
|
adcConversionGroup.chselr = 1 << mux.input; /*no macro to convert N to ADC_CHSELR_CHSEL1*/
|
|
|
|
|
#elif defined(USE_ADCV2)
|
|
|
|
|
adcConversionGroup.sqr3 = ADC_SQR3_SQ1_N(mux.input);
|
2023-01-18 23:30:58 +00:00
|
|
|
#elif defined(RP2040)
|
|
|
|
|
adcConversionGroup.channel_mask = 1 << mux.input;
|
2020-03-11 04:38:39 +00:00
|
|
|
#else
|
2020-03-17 00:29:52 +00:00
|
|
|
adcConversionGroup.sqr[0] = ADC_SQR1_SQ1_N(mux.input);
|
2020-03-11 04:38:39 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
ADCDriver* targetDriver = intToADCDriver(mux.adc);
|
2020-03-17 00:29:52 +00:00
|
|
|
if (!targetDriver) {
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2020-03-11 04:38:39 +00:00
|
|
|
|
2020-03-17 00:29:52 +00:00
|
|
|
manageAdcInitializationDriver(mux.adc, targetDriver);
|
|
|
|
|
if (adcConvert(targetDriver, &adcConversionGroup, &sampleBuffer[0], ADC_BUFFER_DEPTH) != MSG_OK) {
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2020-03-11 04:38:39 +00:00
|
|
|
|
2023-01-18 23:30:58 +00:00
|
|
|
#if defined(USE_ADCV2) || defined(RP2040)
|
2020-03-17 00:29:52 +00:00
|
|
|
// fake 12-bit -> N-bit scale
|
|
|
|
|
return (*sampleBuffer) >> (12 - ADC_RESOLUTION);
|
|
|
|
|
#else
|
|
|
|
|
// already handled as part of adcConvert
|
|
|
|
|
return *sampleBuffer;
|
|
|
|
|
#endif
|
2020-03-11 04:38:39 +00:00
|
|
|
}
|
