mirror of
https://github.com/qmk/qmk_firmware.git
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398 lines
15 KiB
C
398 lines
15 KiB
C
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/*
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LUFA Library
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Copyright (C) Dean Camera, 2017.
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dean [at] fourwalledcubicle [dot] com
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www.lufa-lib.org
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*/
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/*
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Copyright 2017 Dean Camera (dean [at] fourwalledcubicle [dot] com)
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Permission to use, copy, modify, distribute, and sell this
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software and its documentation for any purpose is hereby granted
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without fee, provided that the above copyright notice appear in
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all copies and that both that the copyright notice and this
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permission notice and warranty disclaimer appear in supporting
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documentation, and that the name of the author not be used in
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advertising or publicity pertaining to distribution of the
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software without specific, written prior permission.
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The author disclaims all warranties with regard to this
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software, including all implied warranties of merchantability
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and fitness. In no event shall the author be liable for any
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special, indirect or consequential damages or any damages
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whatsoever resulting from loss of use, data or profits, whether
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in an action of contract, negligence or other tortious action,
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arising out of or in connection with the use or performance of
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this software.
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*/
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/** \file
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* \brief Module Clock Driver for the AVR USB XMEGA microcontrollers.
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*
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* Clock management driver for the AVR USB XMEGA microcontrollers. This driver allows for the configuration
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* of the various clocks within the device to clock the various peripherals.
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*/
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/** \ingroup Group_PlatformDrivers_XMEGA
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* \defgroup Group_PlatformDrivers_XMEGAClocks Clock Management Driver - LUFA/Platform/XMEGA/ClockManagement.h
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* \brief Module Clock Driver for the AVR USB XMEGA microcontrollers.
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*
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* \section Sec_PlatformDrivers_XMEGAClocks_Dependencies Module Source Dependencies
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* The following files must be built with any user project that uses this module:
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* - None
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*
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* \section Sec_PlatformDrivers_XMEGAClocks_ModDescription Module Description
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* Clock management driver for the AVR USB XMEGA microcontrollers. This driver allows for the configuration
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* of the various clocks within the device to clock the various peripherals.
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*
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* Usage Example:
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* \code
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* #include <LUFA/Platform/XMEGA/ClockManagement.h>
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*
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* void main(void)
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* {
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* // Start the PLL to multiply the 2MHz RC oscillator to F_CPU and switch the CPU core to run from it
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* XMEGACLK_StartPLL(CLOCK_SRC_INT_RC2MHZ, 2000000, F_CPU);
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* XMEGACLK_SetCPUClockSource(CLOCK_SRC_PLL);
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*
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* // Start the 32MHz internal RC oscillator and start the DFLL to increase it to F_USB using the USB SOF as a reference
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* XMEGACLK_StartInternalOscillator(CLOCK_SRC_INT_RC32MHZ);
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* XMEGACLK_StartDFLL(CLOCK_SRC_INT_RC32MHZ, DFLL_REF_INT_USBSOF, F_USB);
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* }
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* \endcode
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*
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* @{
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*/
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#ifndef _XMEGA_CLOCK_MANAGEMENT_H_
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#define _XMEGA_CLOCK_MANAGEMENT_H_
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/* Includes: */
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#include "../../Common/Common.h"
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/* Enable C linkage for C++ Compilers: */
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/* Public Interface - May be used in end-application: */
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/* Macros: */
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/** Enum for the possible external oscillator frequency ranges. */
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enum XMEGA_Extern_OSC_ClockFrequency_t
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{
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EXOSC_FREQ_2MHZ_MAX = OSC_FRQRANGE_04TO2_gc, /**< External crystal oscillator equal to or slower than 2MHz. */
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EXOSC_FREQ_9MHZ_MAX = OSC_FRQRANGE_2TO9_gc, /**< External crystal oscillator equal to or slower than 9MHz. */
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EXOSC_FREQ_12MHZ_MAX = OSC_FRQRANGE_9TO12_gc, /**< External crystal oscillator equal to or slower than 12MHz. */
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EXOSC_FREQ_16MHZ_MAX = OSC_FRQRANGE_12TO16_gc, /**< External crystal oscillator equal to or slower than 16MHz. */
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};
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/** Enum for the possible external oscillator startup times. */
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enum XMEGA_Extern_OSC_ClockStartup_t
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{
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EXOSC_START_6CLK = OSC_XOSCSEL_EXTCLK_gc, /**< Wait 6 clock cycles before startup (external clock). */
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EXOSC_START_32KCLK = OSC_XOSCSEL_32KHz_gc, /**< Wait 32K clock cycles before startup (32.768KHz crystal). */
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EXOSC_START_256CLK = OSC_XOSCSEL_XTAL_256CLK_gc, /**< Wait 256 clock cycles before startup. */
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EXOSC_START_1KCLK = OSC_XOSCSEL_XTAL_1KCLK_gc, /**< Wait 1K clock cycles before startup. */
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EXOSC_START_16KCLK = OSC_XOSCSEL_XTAL_16KCLK_gc, /**< Wait 16K clock cycles before startup. */
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};
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/** Enum for the possible module clock sources. */
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enum XMEGA_System_ClockSource_t
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{
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CLOCK_SRC_INT_RC2MHZ = 0, /**< Clock sourced from the Internal 2MHz RC Oscillator clock. */
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CLOCK_SRC_INT_RC32MHZ = 1, /**< Clock sourced from the Internal 32MHz RC Oscillator clock. */
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CLOCK_SRC_INT_RC32KHZ = 2, /**< Clock sourced from the Internal 32KHz RC Oscillator clock. */
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CLOCK_SRC_XOSC = 3, /**< Clock sourced from the External Oscillator clock. */
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CLOCK_SRC_PLL = 4, /**< Clock sourced from the Internal PLL clock. */
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};
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/** Enum for the possible DFLL clock reference sources. */
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enum XMEGA_System_DFLLReference_t
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{
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DFLL_REF_INT_RC32KHZ = 0, /**< Reference clock sourced from the Internal 32KHz RC Oscillator clock. */
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DFLL_REF_EXT_RC32KHZ = 1, /**< Reference clock sourced from the External 32KHz RC Oscillator clock connected to TOSC pins. */
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DFLL_REF_INT_USBSOF = 2, /**< Reference clock sourced from the USB Start Of Frame packets. */
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};
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/* Inline Functions: */
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/** Write a value to a location protected by the XMEGA CCP protection mechanism. This function uses inline assembly to ensure that
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* the protected address is written to within four clock cycles of the CCP key being written.
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*
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* \param[in] Address Address to write to, a memory address protected by the CCP mechanism
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* \param[in] Value Value to write to the protected location
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*/
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static inline void XMEGACLK_CCP_Write(volatile void* Address, const uint8_t Value) ATTR_NON_NULL_PTR_ARG(1) ATTR_ALWAYS_INLINE;
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static inline void XMEGACLK_CCP_Write(volatile void* Address, const uint8_t Value)
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{
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__asm__ __volatile__ (
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"out %0, __zero_reg__" "\n\t" /* Zero RAMPZ using fixed zero value register */
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"movw r30, %1" "\n\t" /* Copy address to Z register pair */
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"out %2, %3" "\n\t" /* Write key to CCP register */
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"st Z, %4" "\n\t" /* Indirectly write value to address */
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: /* No output operands */
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: /* Input operands: */ "m" (RAMPZ), "e" (Address), "m" (CCP), "r" (CCP_IOREG_gc), "r" (Value)
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: /* Clobbered registers: */ "r30", "r31"
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);
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}
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/** Starts the external oscillator of the XMEGA microcontroller, with the given options. This routine blocks until
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* the oscillator is ready for use.
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*
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* \param[in] FreqRange Frequency range of the external oscillator, a value from \ref XMEGA_Extern_OSC_ClockFrequency_t.
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* \param[in] Startup Startup time of the external oscillator, a value from \ref XMEGA_Extern_OSC_ClockStartup_t.
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*
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* \return Boolean \c true if the external oscillator was successfully started, \c false if invalid parameters specified.
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*/
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static inline bool XMEGACLK_StartExternalOscillator(const uint8_t FreqRange,
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const uint8_t Startup) ATTR_ALWAYS_INLINE;
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static inline bool XMEGACLK_StartExternalOscillator(const uint8_t FreqRange,
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const uint8_t Startup)
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{
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OSC.XOSCCTRL = (FreqRange | ((Startup == EXOSC_START_32KCLK) ? OSC_X32KLPM_bm : 0) | Startup);
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OSC.CTRL |= OSC_XOSCEN_bm;
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while (!(OSC.STATUS & OSC_XOSCRDY_bm));
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return true;
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}
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/** Stops the external oscillator of the XMEGA microcontroller. */
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static inline void XMEGACLK_StopExternalOscillator(void) ATTR_ALWAYS_INLINE;
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static inline void XMEGACLK_StopExternalOscillator(void)
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{
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OSC.CTRL &= ~OSC_XOSCEN_bm;
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}
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/** Starts the given internal oscillator of the XMEGA microcontroller, with the given options. This routine blocks until
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* the oscillator is ready for use.
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*
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* \param[in] Source Internal oscillator to start, a value from \ref XMEGA_System_ClockSource_t.
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*
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* \return Boolean \c true if the internal oscillator was successfully started, \c false if invalid parameters specified.
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*/
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static inline bool XMEGACLK_StartInternalOscillator(const uint8_t Source) ATTR_ALWAYS_INLINE;
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static inline bool XMEGACLK_StartInternalOscillator(const uint8_t Source)
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{
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switch (Source)
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{
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case CLOCK_SRC_INT_RC2MHZ:
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OSC.CTRL |= OSC_RC2MEN_bm;
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while (!(OSC.STATUS & OSC_RC2MRDY_bm));
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return true;
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case CLOCK_SRC_INT_RC32MHZ:
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OSC.CTRL |= OSC_RC32MEN_bm;
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while (!(OSC.STATUS & OSC_RC32MRDY_bm));
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return true;
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case CLOCK_SRC_INT_RC32KHZ:
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OSC.CTRL |= OSC_RC32KEN_bm;
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while (!(OSC.STATUS & OSC_RC32KRDY_bm));
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return true;
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default:
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return false;
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}
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}
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/** Stops the given internal oscillator of the XMEGA microcontroller.
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*
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* \param[in] Source Internal oscillator to stop, a value from \ref XMEGA_System_ClockSource_t.
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*
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* \return Boolean \c true if the internal oscillator was successfully stopped, \c false if invalid parameters specified.
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*/
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static inline bool XMEGACLK_StopInternalOscillator(const uint8_t Source) ATTR_ALWAYS_INLINE;
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static inline bool XMEGACLK_StopInternalOscillator(const uint8_t Source)
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{
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switch (Source)
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{
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case CLOCK_SRC_INT_RC2MHZ:
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OSC.CTRL &= ~OSC_RC2MEN_bm;
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return true;
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case CLOCK_SRC_INT_RC32MHZ:
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OSC.CTRL &= ~OSC_RC32MEN_bm;
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return true;
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case CLOCK_SRC_INT_RC32KHZ:
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OSC.CTRL &= ~OSC_RC32KEN_bm;
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return true;
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default:
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return false;
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}
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}
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/** Starts the PLL of the XMEGA microcontroller, with the given options. This routine blocks until the PLL is ready for use.
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*
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* \attention The output frequency must be equal to or greater than the source frequency.
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*
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* \param[in] Source Clock source for the PLL, a value from \ref XMEGA_System_ClockSource_t.
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* \param[in] SourceFreq Frequency of the PLL's clock source, in Hz.
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* \param[in] Frequency Target frequency of the PLL's output.
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*
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* \return Boolean \c true if the PLL was successfully started, \c false if invalid parameters specified.
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*/
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static inline bool XMEGACLK_StartPLL(const uint8_t Source,
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const uint32_t SourceFreq,
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const uint32_t Frequency) ATTR_ALWAYS_INLINE;
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static inline bool XMEGACLK_StartPLL(const uint8_t Source,
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const uint32_t SourceFreq,
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const uint32_t Frequency)
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{
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uint8_t MulFactor = (Frequency / SourceFreq);
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if (SourceFreq > Frequency)
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return false;
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if (MulFactor > 31)
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return false;
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switch (Source)
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{
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case CLOCK_SRC_INT_RC2MHZ:
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OSC.PLLCTRL = (OSC_PLLSRC_RC2M_gc | MulFactor);
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break;
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case CLOCK_SRC_INT_RC32MHZ:
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OSC.PLLCTRL = (OSC_PLLSRC_RC32M_gc | MulFactor);
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break;
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case CLOCK_SRC_XOSC:
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OSC.PLLCTRL = (OSC_PLLSRC_XOSC_gc | MulFactor);
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break;
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default:
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return false;
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}
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OSC.CTRL |= OSC_PLLEN_bm;
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while (!(OSC.STATUS & OSC_PLLRDY_bm));
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return true;
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}
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/** Stops the PLL of the XMEGA microcontroller. */
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static inline void XMEGACLK_StopPLL(void) ATTR_ALWAYS_INLINE;
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static inline void XMEGACLK_StopPLL(void)
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{
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OSC.CTRL &= ~OSC_PLLEN_bm;
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}
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/** Starts the DFLL of the XMEGA microcontroller, with the given options.
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*
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* \param[in] Source RC Clock source for the DFLL, a value from \ref XMEGA_System_ClockSource_t.
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* \param[in] Reference Reference clock source for the DFLL, an value from \ref XMEGA_System_DFLLReference_t.
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* \param[in] Frequency Target frequency of the DFLL's output.
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*
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* \return Boolean \c true if the DFLL was successfully started, \c false if invalid parameters specified.
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*/
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static inline bool XMEGACLK_StartDFLL(const uint8_t Source,
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const uint8_t Reference,
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const uint32_t Frequency) ATTR_ALWAYS_INLINE;
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static inline bool XMEGACLK_StartDFLL(const uint8_t Source,
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const uint8_t Reference,
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const uint32_t Frequency)
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{
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uint16_t DFLLCompare = (Frequency / 1024);
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switch (Source)
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{
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case CLOCK_SRC_INT_RC2MHZ:
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OSC.DFLLCTRL |= (Reference << OSC_RC2MCREF_bp);
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DFLLRC2M.COMP1 = (DFLLCompare & 0xFF);
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DFLLRC2M.COMP2 = (DFLLCompare >> 8);
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DFLLRC2M.CTRL = DFLL_ENABLE_bm;
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break;
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case CLOCK_SRC_INT_RC32MHZ:
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OSC.DFLLCTRL |= (Reference << OSC_RC32MCREF_gp);
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DFLLRC32M.COMP1 = (DFLLCompare & 0xFF);
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DFLLRC32M.COMP2 = (DFLLCompare >> 8);
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if (Reference == DFLL_REF_INT_USBSOF)
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{
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NVM.CMD = NVM_CMD_READ_CALIB_ROW_gc;
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DFLLRC32M.CALA = pgm_read_byte(offsetof(NVM_PROD_SIGNATURES_t, USBRCOSCA));
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DFLLRC32M.CALB = pgm_read_byte(offsetof(NVM_PROD_SIGNATURES_t, USBRCOSC));
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NVM.CMD = 0;
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}
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DFLLRC32M.CTRL = DFLL_ENABLE_bm;
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break;
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default:
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return false;
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}
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return true;
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}
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/** Stops the given DFLL of the XMEGA microcontroller.
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*
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* \param[in] Source RC Clock source for the DFLL to be stopped, a value from \ref XMEGA_System_ClockSource_t.
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*
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||
|
|
* \return Boolean \c true if the DFLL was successfully stopped, \c false if invalid parameters specified.
|
||
|
|
*/
|
||
|
|
static inline bool XMEGACLK_StopDFLL(const uint8_t Source) ATTR_ALWAYS_INLINE;
|
||
|
|
static inline bool XMEGACLK_StopDFLL(const uint8_t Source)
|
||
|
|
{
|
||
|
|
switch (Source)
|
||
|
|
{
|
||
|
|
case CLOCK_SRC_INT_RC2MHZ:
|
||
|
|
DFLLRC2M.CTRL = 0;
|
||
|
|
break;
|
||
|
|
case CLOCK_SRC_INT_RC32MHZ:
|
||
|
|
DFLLRC32M.CTRL = 0;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
/** Sets the clock source for the main microcontroller core. The given clock source should be configured
|
||
|
|
* and ready for use before this function is called.
|
||
|
|
*
|
||
|
|
* \param[in] Source Clock source for the CPU core, a value from \ref XMEGA_System_ClockSource_t.
|
||
|
|
*
|
||
|
|
* \return Boolean \c true if the CPU core clock was successfully altered, \c false if invalid parameters specified.
|
||
|
|
*/
|
||
|
|
static inline bool XMEGACLK_SetCPUClockSource(const uint8_t Source) ATTR_ALWAYS_INLINE;
|
||
|
|
static inline bool XMEGACLK_SetCPUClockSource(const uint8_t Source)
|
||
|
|
{
|
||
|
|
uint8_t ClockSourceMask = 0;
|
||
|
|
|
||
|
|
switch (Source)
|
||
|
|
{
|
||
|
|
case CLOCK_SRC_INT_RC2MHZ:
|
||
|
|
ClockSourceMask = CLK_SCLKSEL_RC2M_gc;
|
||
|
|
break;
|
||
|
|
case CLOCK_SRC_INT_RC32MHZ:
|
||
|
|
ClockSourceMask = CLK_SCLKSEL_RC32M_gc;
|
||
|
|
break;
|
||
|
|
case CLOCK_SRC_INT_RC32KHZ:
|
||
|
|
ClockSourceMask = CLK_SCLKSEL_RC32K_gc;
|
||
|
|
break;
|
||
|
|
case CLOCK_SRC_XOSC:
|
||
|
|
ClockSourceMask = CLK_SCLKSEL_XOSC_gc;
|
||
|
|
break;
|
||
|
|
case CLOCK_SRC_PLL:
|
||
|
|
ClockSourceMask = CLK_SCLKSEL_PLL_gc;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
uint_reg_t CurrentGlobalInt = GetGlobalInterruptMask();
|
||
|
|
GlobalInterruptDisable();
|
||
|
|
|
||
|
|
XMEGACLK_CCP_Write(&CLK.CTRL, ClockSourceMask);
|
||
|
|
|
||
|
|
SetGlobalInterruptMask(CurrentGlobalInt);
|
||
|
|
|
||
|
|
Delay_MS(1);
|
||
|
|
return (CLK.CTRL == ClockSourceMask);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Disable C linkage for C++ Compilers: */
|
||
|
|
#if defined(__cplusplus)
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/** @} */
|
||
|
|
|